summaryrefslogtreecommitdiffstats
path: root/src/include/device/pci_ops.h
diff options
context:
space:
mode:
authorRonald G. Minnich <rminnich@gmail.com>2012-07-02 09:41:10 -0700
committerSven Schnelle <svens@stackframe.org>2012-07-05 23:01:42 +0200
commit97de28da8af758b85c644b3dc151aeb743e13412 (patch)
tree11823473dd850f8cdaf0be2b97cef64ddfb30d8f /src/include/device/pci_ops.h
parent63539bb9d7fe9ae55a364cadfcbd79ecb98a9412 (diff)
downloadcoreboot-97de28da8af758b85c644b3dc151aeb743e13412.tar.gz
coreboot-97de28da8af758b85c644b3dc151aeb743e13412.tar.bz2
coreboot-97de28da8af758b85c644b3dc151aeb743e13412.zip
PCI Type2 config must die
PCI Type 2 config was a strange and never-used config mechanism. It is unlikely that in the 13 years of coreboot's existence that type 2 was ever used; it just made life complicated for everyone. It lived long enough in coreboot to be replaced by mmioconf. Prior to making the device tree visible in romstage we want to get rid of type2. Delete two files we don't need any more (yay!). Replace two functions with one: pci_config_default, which returns a pointer to the default config method. At some future time this may change to mmio but for now it is old type1 style. Change-Id: Icc4ccf379a89bfca8be43f305b68ab45d88bf0ab Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1159 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
Diffstat (limited to 'src/include/device/pci_ops.h')
-rw-r--r--src/include/device/pci_ops.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h
index e5e54b6d4df8..2efbf9da4950 100644
--- a/src/include/device/pci_ops.h
+++ b/src/include/device/pci_ops.h
@@ -21,7 +21,4 @@ void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val);
void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val);
#endif
-/* This function lives in pci_ops_auto.c */
-const struct pci_bus_operations *pci_remember_direct(void);
-
#endif /* PCI_OPS_H */