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| author | Subrata Banik <subrata.banik@intel.com> | 2019-03-25 21:49:39 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-03-27 04:39:48 +0000 |
| commit | ed6996f2babb6efd794e45e18f39a09d2996b2b0 (patch) | |
| tree | ee5b96b7cf4560ff3d307fdddaccb2466c4b2061 /src/include/device/pciexp.h | |
| parent | e651e01518d904bf661db90fb986af82db04a843 (diff) | |
| download | coreboot-ed6996f2babb6efd794e45e18f39a09d2996b2b0.tar.gz coreboot-ed6996f2babb6efd794e45e18f39a09d2996b2b0.tar.bz2 coreboot-ed6996f2babb6efd794e45e18f39a09d2996b2b0.zip | |
device/pciexp_device: Convert LTR non-snoop/snoop value into common macro
Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/include/device/pciexp.h')
| -rw-r--r-- | src/include/device/pciexp.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 0f1420a0133a..3a9825d87173 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -14,6 +14,11 @@ enum aspm_type { #define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29 #define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET) +/* Latency tolerance reporting, max non-snoop latency value 3.14ms */ +#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US 0x1003 +/* Latency tolerance reporting, max snoop latency value 3.14ms */ +#define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003 + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); |