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| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-09-14 11:57:42 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-18 13:11:11 +0000 |
| commit | 2eb7c43491bfea5c2940a7f877ae6f3b8b373dad (patch) | |
| tree | e041b265a3d0d745062e0c567d2ae8d1316fe08f /src/include/device | |
| parent | 9ba52321b5b25cc297bd89ae2b8666eff697d374 (diff) | |
| download | coreboot-2eb7c43491bfea5c2940a7f877ae6f3b8b373dad.tar.gz coreboot-2eb7c43491bfea5c2940a7f877ae6f3b8b373dad.tar.bz2 coreboot-2eb7c43491bfea5c2940a7f877ae6f3b8b373dad.zip | |
soc/intel: Update Raptor Lake graphics device IDs
Added Raptor Lake U graphics device ids.
Renamed Raptor Lake U graphics device ids that were marked as
Raptor Lake P.
Added Raptor Lake P graphics device ids.
References:
RaptorLake External Design Specification Volume 1 (640555)
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I44734f927764f872b89e3805a47d16c1ffa28865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77898
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ea7841f0ef6e..e2836c8cf80d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4060,9 +4060,13 @@ #define PCI_DID_INTEL_RPL_P_GT1 0xa720 #define PCI_DID_INTEL_RPL_P_GT2 0xa7a8 #define PCI_DID_INTEL_RPL_P_GT3 0xa7a0 -#define PCI_DID_INTEL_RPL_P_GT4 0xa7a9 -#define PCI_DID_INTEL_RPL_P_GT5 0xa7a1 -#define PCI_DID_INTEL_RPL_P_GT6 0xa721 +#define PCI_DID_INTEL_RPL_P_GT4 0xa7aa +#define PCI_DID_INTEL_RPL_P_GT5 0xa7ab +#define PCI_DID_INTEL_RPL_U_GT1 0xa7a9 +#define PCI_DID_INTEL_RPL_U_GT2 0xa7a1 +#define PCI_DID_INTEL_RPL_U_GT3 0xa721 +#define PCI_DID_INTEL_RPL_U_GT4 0xa7ac +#define PCI_DID_INTEL_RPL_U_GT5 0xa7ad /* Intel Northbridge Ids */ #define PCI_DID_INTEL_APL_NB 0x5af0 |