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| author | Max Fritz <antischmock@googlemail.com> | 2022-11-19 01:54:44 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-12 13:52:16 +0000 |
| commit | 573e6ded9f0cc0119c90dbe849480b1a2974773e (patch) | |
| tree | 6d19b2c5fba0bdb210c26316f8f86b5907131ab4 /src/include/device | |
| parent | 5787bd21c7f61d983dfcd6ef90cd5c6b6f10f33a (diff) | |
| download | coreboot-573e6ded9f0cc0119c90dbe849480b1a2974773e.tar.gz coreboot-573e6ded9f0cc0119c90dbe849480b1a2974773e.tar.bz2 coreboot-573e6ded9f0cc0119c90dbe849480b1a2974773e.zip | |
soc/intel/alderlake: Add support for Raptor Lake S CPUs
Add PCI IDs, default VR values and power limits for Raptor Lake S
CPUs. Based on docs 639116 and 640555.
TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu
22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P
with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04.
Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155
Signed-off-by: Max Fritz <antischmock@googlemail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 418f9e09dc28..939f71722cd1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4048,6 +4048,10 @@ #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50 #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 +#define PCI_DID_INTEL_RPL_S_GT0 0xa79f +#define PCI_DID_INTEL_RPL_S_GT1_1 0xa780 +#define PCI_DID_INTEL_RPL_S_GT1_2 0xa782 +#define PCI_DID_INTEL_RPL_S_GT1_3 0xa783 #define PCI_DID_INTEL_RPL_P_GT1 0xa720 #define PCI_DID_INTEL_RPL_P_GT2 0xa7a8 #define PCI_DID_INTEL_RPL_P_GT3 0xa7a0 @@ -4173,6 +4177,11 @@ #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 #define PCI_DID_INTEL_MTL_P_ID_5 0x7d16 +#define PCI_DID_INTEL_RPL_S_ID_1 0xa700 +#define PCI_DID_INTEL_RPL_S_ID_2 0xa701 +#define PCI_DID_INTEL_RPL_S_ID_3 0xa703 +#define PCI_DID_INTEL_RPL_S_ID_4 0xa704 +#define PCI_DID_INTEL_RPL_S_ID_5 0xa705 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 |