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| author | Martin Roth <gaumless@gmail.com> | 2023-10-23 09:59:09 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-25 14:06:37 +0000 |
| commit | 58964ff02ce7a78bc698f424fd0834aad930e1af (patch) | |
| tree | 248869b0b05c00a54d33a93500f4dceb4315453e /src/include/device | |
| parent | 7039edd2da302bb63dc8930a8492b5d6940d7e33 (diff) | |
| download | coreboot-58964ff02ce7a78bc698f424fd0834aad930e1af.tar.gz coreboot-58964ff02ce7a78bc698f424fd0834aad930e1af.tar.bz2 coreboot-58964ff02ce7a78bc698f424fd0834aad930e1af.zip | |
include/device/dram: Add SPD lengths for DDR3 to DDR5
DDR2 already had a define to specify the SPD length, but other memory
types did not. This led to the value being coded into other locations.
Unify the definition for DDR2 to DDR5 and put the value at the top of
the respective header file.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id13b9c5d311984d4a98b831a8746d1659724aa96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/dram/ddr2.h | 6 | ||||
| -rw-r--r-- | src/include/device/dram/ddr3.h | 3 | ||||
| -rw-r--r-- | src/include/device/dram/ddr4.h | 3 | ||||
| -rw-r--r-- | src/include/device/dram/ddr5.h | 3 |
4 files changed, 12 insertions, 3 deletions
diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 9277ffbc028d..032d5ce4cc83 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -18,6 +18,9 @@ #include <spd.h> #include <device/dram/common.h> +/** Maximum SPD size supported */ +#define SPD_SIZE_MAX_DDR2 128 + /* Byte 20 [5:0]: DDR2 Module type information */ enum spd_dimm_type_ddr2 { SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00, @@ -151,9 +154,6 @@ struct dimm_attr_ddr2_st { u32 serial; }; -/** Maximum SPD size supported */ -#define SPD_SIZE_MAX_DDR2 128 - int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type); u8 spd_ddr2_calc_checksum(u8 *spd, int len); u32 spd_decode_spd_size_ddr2(u8 byte0); diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 8886e64ac820..6efe0494dfbf 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -19,6 +19,9 @@ #include <device/dram/common.h> #include <types.h> +/** Maximum SPD size supported */ +#define SPD_SIZE_MAX_DDR3 256 + /** * Convenience definitions for SPD offsets * diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index 6b05288fd777..72102125206e 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -18,6 +18,9 @@ #include <device/dram/common.h> #include <types.h> +/** Maximum SPD size supported */ +#define SPD_SIZE_MAX_DDR4 512 + #define SPD_DDR4_PART_OFF 329 #define SPD_DDR4_PART_LEN 20 diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h index a50912637154..ff1604a808a4 100644 --- a/src/include/device/dram/ddr5.h +++ b/src/include/device/dram/ddr5.h @@ -12,6 +12,9 @@ #include <device/dram/common.h> #include <types.h> +/** Maximum SPD size supported */ +#define SPD_SIZE_MAX_DDR5 1024 + /** * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s */ |