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| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2021-07-24 14:50:36 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-11-29 03:19:51 +0000 |
| commit | 777ffff4421a9ab0961f2284e7448307f3c5154f (patch) | |
| tree | f6108138ca5fe3f73025a2a8374c0588a386673b /src/include/device | |
| parent | 60df92fdce147b56ba5e830f962435589dbd258b (diff) | |
| download | coreboot-777ffff4421a9ab0961f2284e7448307f3c5154f.tar.gz coreboot-777ffff4421a9ab0961f2284e7448307f3c5154f.tar.bz2 coreboot-777ffff4421a9ab0961f2284e7448307f3c5154f.zip | |
device/pci_device.c: Scan only one device for PCIe
Only scan one device if it's a PCIe downstream port.
A PCIe downstream port normally leads to a link with only device 0 on
it. As an optimization, scan only for device 0 in that case.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_def.h | 1 | ||||
| -rw-r--r-- | src/include/device/pciexp.h | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 22a5390e0527..06114363f624 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -385,6 +385,7 @@ #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ +#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 014fcb18b19f..fbc769e7c68a 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -31,4 +31,12 @@ void pciexp_hotplug_scan_bridge(struct device *dev); extern struct device_operations default_pciexp_hotplug_ops_bus; unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap); + +static inline bool pciexp_is_downstream_port(int type) +{ + return type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_DOWNSTREAM || + type == PCI_EXP_TYPE_PCIE_BRIDGE; +} + #endif /* DEVICE_PCIEXP_H */ |