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| author | Chia-Ling Hou <chia-ling.hou@intel.com> | 2023-06-07 16:53:00 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-23 15:22:45 +0000 |
| commit | b5a032859aec1449b46eed60a6c6aeb9147e45a7 (patch) | |
| tree | 1fe057507bc9193485619a060990ebddc5ba8f9c /src/include/device | |
| parent | 3dedfcbbd472fe569e06e8454db77fa8915a0a2f (diff) | |
| download | coreboot-b5a032859aec1449b46eed60a6c6aeb9147e45a7.tar.gz coreboot-b5a032859aec1449b46eed60a6c6aeb9147e45a7.tar.bz2 coreboot-b5a032859aec1449b46eed60a6c6aeb9147e45a7.zip | |
soc/intel/jasperlake: Add per-SKU power limits
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.
BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Super Ni <super.ni@intel.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 40df09008803..418f9e09dc28 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4135,6 +4135,7 @@ #define PCI_DID_INTEL_JSL_ID_3 0x4e12 #define PCI_DID_INTEL_JSL_ID_4 0x4e14 #define PCI_DID_INTEL_JSL_ID_5 0x4e24 +#define PCI_DID_INTEL_JSL_ID_6 0x4e28 #define PCI_DID_INTEL_ADL_S_ID_1 0x4660 #define PCI_DID_INTEL_ADL_S_ID_2 0x4664 |