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| author | Tristan Corrick <tristan@corrick.kiwi> | 2018-12-06 22:46:58 +1300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-28 12:22:35 +0000 |
| commit | d3f01b21fa7bf9bf115088ddc032aa1cd0000945 (patch) | |
| tree | 38bffbac06c031deb871931c3393efc4f732a8c2 /src/include/device | |
| parent | c54d52d67d89fbd31f0723468737c62d7f97442f (diff) | |
| download | coreboot-d3f01b21fa7bf9bf115088ddc032aa1cd0000945.tar.gz coreboot-d3f01b21fa7bf9bf115088ddc032aa1cd0000945.tar.bz2 coreboot-d3f01b21fa7bf9bf115088ddc032aa1cd0000945.zip | |
sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports
The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root
ports, all others have 8 [1]. The existing PCIe code assumed that all
non-LP chipsets had 8 root ports, which meant that port 6 would not be
considered the last root port on H81, so `root_port_commit_config()`
would not run. Ultimately, while PCIe still worked on H81, all the root
ports would remain enabled, even if disabled in the devicetree.
Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they
are unused, and the MAX constant is incorrect.
Interestingly, this fixes an issue where GRUB is unable to halt the
system.
Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree
do indeed end up disabled.
[1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub
(PCH) Datasheet, revision 003, document number 328904.
Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30077
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b9c915239d77..751cca0289c6 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2661,11 +2661,26 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 -/* Intel Lynx Point Device IDS */ -#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN 0x8c41 -#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX 0x8c4f - /* Intel LPC device ids */ +#define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 +#define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 +#define PCI_DEVICE_ID_INTEL_LPT_Z87 0x8c44 +#define PCI_DEVICE_ID_INTEL_LPT_Z85 0x8c46 +#define PCI_DEVICE_ID_INTEL_LPT_HM86 0x8c49 +#define PCI_DEVICE_ID_INTEL_LPT_H87 0x8c4a +#define PCI_DEVICE_ID_INTEL_LPT_HM87 0x8c4b +#define PCI_DEVICE_ID_INTEL_LPT_Q85 0x8c4c +#define PCI_DEVICE_ID_INTEL_LPT_Q87 0x8c4e +#define PCI_DEVICE_ID_INTEL_LPT_QM87 0x8c4f +#define PCI_DEVICE_ID_INTEL_LPT_B85 0x8c50 +#define PCI_DEVICE_ID_INTEL_LPT_C222 0x8c52 +#define PCI_DEVICE_ID_INTEL_LPT_C224 0x8c54 +#define PCI_DEVICE_ID_INTEL_LPT_C226 0x8c56 +#define PCI_DEVICE_ID_INTEL_LPT_H81 0x8c5c +#define PCI_DEVICE_ID_INTEL_LPT_LP_SAMPLE 0x9c41 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PREMIUM 0x9c43 +#define PCI_DEVICE_ID_INTEL_LPT_LP_MAINSTREAM 0x9c45 +#define PCI_DEVICE_ID_INTEL_LPT_LP_VALUE 0x9c47 #define PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE 0x9d41 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48 |