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| author | Furquan Shaikh <furquan@chromium.org> | 2016-11-05 23:57:02 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-11-10 00:50:23 +0100 |
| commit | cab1c01885e216027086b20c6b0628df7383f487 (patch) | |
| tree | 04bd15dadb36f52fedc4e0a152fa5947f2157793 /src/include/elog.h | |
| parent | 470852bb0898b07630b03d8246b9232fa84fe4de (diff) | |
| download | coreboot-cab1c01885e216027086b20c6b0628df7383f487.tar.gz coreboot-cab1c01885e216027086b20c6b0628df7383f487.tar.bz2 coreboot-cab1c01885e216027086b20c6b0628df7383f487.zip | |
mrc: Add support for separate training cache in recovery mode
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or
RECOVERY_MRC_CACHE based on the boot mode.
- If normal mode boot, use RW_MRC_CACHE, if available.
- If recovery mode boot:
- Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is
requested explicity with retrain memory request.
- Use RECOVERY_MRC_CACHE otherwise.
2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot
modes. Check if both are present under one unified region and protect
that region as a whole. Else try protecting individual regions.
3. Update training data in appropriate cache:
- Use RW_MRC_CACHE if normal mode.
- Use RECOVERY_MRC_CACHE if present in recovery mode. Else use
RW_MRC_CACHE.
4. Add proper debug logs to indicate which training data cache is used
at any point.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified that correct cache is used in both normal and recovery
mode on reef.
Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17242
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/elog.h')
| -rw-r--r-- | src/include/elog.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/elog.h b/src/include/elog.h index 7fdcda71a75a..fec9d091e98c 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -152,6 +152,7 @@ struct elog_event_data_me_extended { /* Memory Cache Update */ #define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa #define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 #define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 #define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 struct elog_event_mem_cache_update { |