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| author | Furquan Shaikh <furquan@google.com> | 2014-08-26 15:39:51 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-28 07:05:09 +0100 |
| commit | abde3b56cebc611391a3e3ec63172acefea4daae (patch) | |
| tree | 3aa00bea4e70a5303a7a8d8ddf7a9772217743b9 /src/include/rules.h | |
| parent | ab020f304efdac61d38876a95005d8478659faae (diff) | |
| download | coreboot-abde3b56cebc611391a3e3ec63172acefea4daae.tar.gz coreboot-abde3b56cebc611391a3e3ec63172acefea4daae.tar.bz2 coreboot-abde3b56cebc611391a3e3ec63172acefea4daae.zip | |
arm64: Add support for secure monitor
Secure monitor runs at EL3 and is responsible for jumping to the payload at
specified EL and also to manage features like PSCI.
Adding basic implementation of secure monitor as a rmodule. Currently, it just
jumps to the the payload at current EL. Support for switching el and PSCI will
be added as separate patches.
CQ-DEPEND=CL:218300
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles succesfully and secure monitor loads and runs payload on ryu
Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34
Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214371
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9080
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include/rules.h')
| -rw-r--r-- | src/include/rules.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/include/rules.h b/src/include/rules.h index 22111e8dfb27..5740b77a4a82 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -28,24 +28,35 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 +#define ENV_SECMON 0 #elif defined(__PRE_RAM__) #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 1 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 +#define ENV_SECMON 0 #elif defined(__SMM__) #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 1 -#else +#define ENV_SECMON 0 +#elif defined(__SECMON__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 1 + +#else #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 1 #define ENV_SMM 0 +#define ENV_SECMON 0 #endif /* For romstage and ramstage always build with simple device model, ie. |