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| author | Julius Werner <jwerner@chromium.org> | 2019-08-16 15:35:39 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 10:10:48 +0000 |
| commit | f96d9051c2b39544300d35f64ce92502e1e230c0 (patch) | |
| tree | 141966be0dedd056261528e55e05efde4b20b56d /src/include/rules.h | |
| parent | 63c444a69b98bc8a86719699423b3273cc5759e8 (diff) | |
| download | coreboot-f96d9051c2b39544300d35f64ce92502e1e230c0.tar.gz coreboot-f96d9051c2b39544300d35f64ce92502e1e230c0.tar.bz2 coreboot-f96d9051c2b39544300d35f64ce92502e1e230c0.zip | |
Remove MIPS architecture
The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.
Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/rules.h')
| -rw-r--r-- | src/include/rules.h | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/src/include/rules.h b/src/include/rules.h index 0436198363e1..9e13ee65a64d 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -173,7 +173,6 @@ #define ENV_ARMV7 0 #endif #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 0 #define ENV_X86_32 0 @@ -189,19 +188,6 @@ #else #define ENV_ARMV8 0 #endif -#define ENV_MIPS 0 -#define ENV_RISCV 0 -#define ENV_X86 0 -#define ENV_X86_32 0 -#define ENV_X86_64 0 - -#elif defined(__ARCH_mips__) -#define ENV_ARM 0 -#define ENV_ARM64 0 -#define ENV_ARMV4 0 -#define ENV_ARMV7 0 -#define ENV_ARMV8 0 -#define ENV_MIPS 1 #define ENV_RISCV 0 #define ENV_X86 0 #define ENV_X86_32 0 @@ -213,7 +199,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 1 #define ENV_X86 0 #define ENV_X86_32 0 @@ -225,7 +210,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 1 #define ENV_X86_32 1 @@ -237,7 +221,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 1 #define ENV_X86_32 0 @@ -249,7 +232,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 0 #define ENV_X86_32 0 |