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| author | Ed Swierk <eswierk@arastra.com> | 2008-08-28 18:23:58 +0000 |
|---|---|---|
| committer | Ed Swierk <eswierk@arastra.com> | 2008-08-28 18:23:58 +0000 |
| commit | d39aad932385d46f67008f5fa3ad8c83c995bb99 (patch) | |
| tree | b1c2828450a1047a2fe08bf6fcbbb5c11d484ee0 /src/include/spd.h | |
| parent | 7eda890d9af652558b0e710b9d17c8915ab3421a (diff) | |
| download | coreboot-d39aad932385d46f67008f5fa3ad8c83c995bb99.tar.gz coreboot-d39aad932385d46f67008f5fa3ad8c83c995bb99.tar.bz2 coreboot-d39aad932385d46f67008f5fa3ad8c83c995bb99.zip | |
Add definitions for DDR2 SPD registers.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/spd.h')
| -rw-r--r-- | src/include/spd.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/include/spd.h b/src/include/spd.h index e04ad7ae1efc..53031c12e447 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -74,6 +74,16 @@ #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */ #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */ #define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */ +#define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */ +#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */ +#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */ +#define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */ +#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */ +#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */ +#define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */ +#define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */ +#define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */ +#define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */ #define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */ #define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */ #define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */ |