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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-03-13 17:16:20 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 12:56:01 +0000 |
| commit | cb1e386eabfbf2d0851ed58f97d11a7bab431983 (patch) | |
| tree | e2f5c0ade2e493d464b0d1531d421d6dacd23648 /src/include/spd_bin.h | |
| parent | a6bff2d8ab4824a95221fda8a3b175c3f4337720 (diff) | |
| download | coreboot-cb1e386eabfbf2d0851ed58f97d11a7bab431983.tar.gz coreboot-cb1e386eabfbf2d0851ed58f97d11a7bab431983.tar.bz2 coreboot-cb1e386eabfbf2d0851ed58f97d11a7bab431983.zip | |
lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs
Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/include/spd_bin.h')
| -rw-r--r-- | src/include/spd_bin.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index c78f7c326704..fb771f2bf80a 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -29,6 +29,9 @@ #define SPD_DRAM_LPDDR3_JEDEC 0x0F #define SPD_DRAM_DDR4 0x0C #define SPD_DRAM_LPDDR4 0x10 +#define SPD_DRAM_LPDDR4X 0x11 +#define SPD_DRAM_DDR5 0x12 +#define SPD_DRAM_LPDDR5 0x13 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define DDR3_ORGANIZATION 7 |