lib/spd_cache: add spd_cache common code

This patch adds some spd_cache functions. They are for implementing the
spd_cache. It's for reducing the SPD fetch time when device uses SODIMMs.
The MRC cache also includes SPD data, but there is no public header file
available to decode the struct of MRC. So SPD cache is another solution.

BUG=b:146457985
BRANCH=None
TEST=Build puff successfully and verified below two items.
     one DIMM save the boot time : 158ms
     two DIMM save the boot time : 265ms

Change-Id: Ia48aa022fabf8949960a50597185c9d821399522
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

1 files changed, 23 insertions, 0 deletions

diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h
new file mode 100644
index 000000000000..3270defba85c
--- /dev/null
+++ b/src/include/spd_cache.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef __SPD_CACHE_H
+#define __SPD_CACHE_H
+
+#include <spd_bin.h>
+
+#define SPD_CACHE_FMAP_NAME	"RW_SPD_CACHE"
+#define SC_SPD_NUMS		(CONFIG_DIMM_MAX)
+#define SC_SPD_OFFSET(n)	(CONFIG_DIMM_SPD_SIZE * n)
+#define SC_CRC_OFFSET		(CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE)
+#define SC_SPD_TOTAL_LEN	(CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE)
+#define SC_SPD_LEN		(CONFIG_DIMM_SPD_SIZE)
+#define SC_CRC_LEN		(sizeof(uint16_t))
+
+enum cb_err update_spd_cache(struct spd_block *blk);
+enum cb_err load_spd_cache(uint8_t **spd_cache, size_t *spd_cache_sz);
+bool spd_cache_is_valid(uint8_t *spd_cache, size_t spd_cache_sz);
+bool check_if_dimm_changed(u8 *spd_cache, struct spd_block *blk);
+enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk);
+
+#endif