drivers: spi_flash: Add Fast Read Dual I/O support

The Fast Read Dual Output and Fast Read Dual I/O commands are
practically identical, the only difference being how the read address is
transferred (saving a whooping 2 bytes which is totally irrelevant for
the amounts of data coreboot tends to read). We originally implemented
Fast Read Dual Output since it's the older command and some older
Winbond chips only supported that one... but it seems that some older
Macronix parts for whatever reason chose to only support Fast Read Dual
I/O instead. So in order to make this work for as many parts as
possible, I guess we'll have to implement both. (Also, the Macronix
device ID situation is utter madness with different chips with different
capabilities often having the same ID, so we basically have to make a
best-effort guess to strike a trade-off between fast speeds and best
chance at supporting all chips. If this turns out to be a problem later,
we may have to add Kconfig overrides for this or resort to SFDP parsing,
although that would defeat the whole point of trying to be fast.)

BUG=b:193486682
TEST=Booted CoachZ (with Dual I/O)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index a7f707eb1c4c..fe77e3ef794c 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -86,8 +86,9 @@ struct spi_flash {
 	union {
 		u8 raw;
 		struct {
-			u8 dual_spi	: 1;
-			u8 _reserved	: 7;
+			u8 dual_output	: 1;
+			u8 dual_io	: 1;
+			u8 _reserved	: 6;
 		};
 	} flags;
 	u16 model;