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| author | Subrata Banik <subrata.banik@intel.com> | 2019-07-29 14:21:55 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-08-02 04:34:55 +0000 |
| commit | 06cc764483d1220aeed28ff1097e6d517f51b0dd (patch) | |
| tree | f463951b0ab2e6aa2a3ecca209d7a1a597a322f2 /src/include/stage_cache.h | |
| parent | ed9ea86ba34252bcd1cd7b6f027d2ff9fe3b6d6b (diff) | |
| download | coreboot-06cc764483d1220aeed28ff1097e6d517f51b0dd.tar.gz coreboot-06cc764483d1220aeed28ff1097e6d517f51b0dd.tar.bz2 coreboot-06cc764483d1220aeed28ff1097e6d517f51b0dd.zip | |
soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usage
This patch overrides EnableTcoTimer FSP UPD default value based on
PmTimerDisabled coreboot devcietree config.
BRANCH=none
BUG=b:138152075
Change-Id: I347c15c7b65fb4c19b9680f127980d4ddab8df51
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/include/stage_cache.h')
0 files changed, 0 insertions, 0 deletions