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| author | Subrata Banik <subrata.banik@intel.com> | 2018-02-06 15:25:27 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-02-07 08:09:24 +0000 |
| commit | ac1cd44525d7230a0138fdd3e442ad8b1363c4dc (patch) | |
| tree | e6e14f73366aa60a04cf05781d71022ff1f3067a /src/include/stage_cache.h | |
| parent | 828c39eb6ba4aa72ffb027a0fc70d8ec78a83d24 (diff) | |
| download | coreboot-ac1cd44525d7230a0138fdd3e442ad8b1363c4dc.tar.gz coreboot-ac1cd44525d7230a0138fdd3e442ad8b1363c4dc.tar.bz2 coreboot-ac1cd44525d7230a0138fdd3e442ad8b1363c4dc.zip | |
soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig for CNP-PCH
This patch ensures soc/sata.c correctly translates pci config offset 0x92
Bit 0-2 [SATA Port x Present (SPDx)]
0 = Port x is enabled.
1 = Port x is disabled.
Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/include/stage_cache.h')
0 files changed, 0 insertions, 0 deletions