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| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-09-07 10:33:30 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-09-12 08:12:02 +0000 |
| commit | 1eff77bc59b77735872e675a8df4f059245e4be7 (patch) | |
| tree | 6a09a4c448c22e5c6f97138d88526a4a00f5e971 /src/include | |
| parent | a6a5b25ce4235c4e645d3dc20f8222b1a81c54a3 (diff) | |
| download | coreboot-1eff77bc59b77735872e675a8df4f059245e4be7.tar.gz coreboot-1eff77bc59b77735872e675a8df4f059245e4be7.tar.bz2 coreboot-1eff77bc59b77735872e675a8df4f059245e4be7.zip | |
arch/x86: Reduce max phys address size for Intel TME capable SoCs
On Intel SoCs, if TME is supported, TME key ID bits are reserved and
should be subtracted from the maximum physical addresses available.
BUG=288978352
TEST=Verified that DMAR ACPI table `Host Address Width` field on rex
went from 45 to 41.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/intel/msr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 8efe4e2c62e3..75c12a8be951 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -33,4 +33,7 @@ #define MSR_PKG_C10_RESIDENCY 0x632 +#define MSR_TME_ACTIVATE 0x982 +#define TME_ACTIVATE_HI_KEYID_BITS_MASK 0xf + #endif /* CPU_INTEL_MSR_H */ |