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| author | zhixingma <zhixing.ma@intel.com> | 2022-06-13 15:06:27 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-28 21:01:27 +0000 |
| commit | 529a64b788888aa21189104309a5e9e814bcb0e0 (patch) | |
| tree | 4d296c1b555fed9bc70dd9f884c79e14c7aa31ce /src/include | |
| parent | dd582b0cb10932fae8198c928172af49deeab34e (diff) | |
| download | coreboot-529a64b788888aa21189104309a5e9e814bcb0e0.tar.gz coreboot-529a64b788888aa21189104309a5e9e814bcb0e0.tar.bz2 coreboot-529a64b788888aa21189104309a5e9e814bcb0e0.zip | |
soc/intel: Add Raptor Lake device IDs
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs.
References:
RaptorLake External Design Specification Volume 1 (640555)
600/700 Series PCH External Design Specification Volume 1 (626817)
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on adlrvp + rpl silicon
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/intel/cpu_ids.h | 1 | ||||
| -rw-r--r-- | src/include/device/pci_ids.h | 5 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index d8191331d93c..bb5511f126b6 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -64,5 +64,6 @@ #define CPUID_METEORLAKE_A0_1 0xa06a0 #define CPUID_METEORLAKE_A0_2 0xa06a1 #define CPUID_RAPTORLAKE_P_J0 0xb06a2 +#define CPUID_RAPTORLAKE_P_Q0 0xb06a3 #endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c997da44b4fd..429a89bb2c1a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4013,7 +4013,9 @@ #define PCI_DID_INTEL_RPL_P_GT1 0xa720 #define PCI_DID_INTEL_RPL_P_GT2 0xa7a8 #define PCI_DID_INTEL_RPL_P_GT3 0xa7a0 - +#define PCI_DID_INTEL_RPL_P_GT4 0xa7a9 +#define PCI_DID_INTEL_RPL_P_GT5 0xa7a1 +#define PCI_DID_INTEL_RPL_P_GT6 0xa721 /* Intel Northbridge Ids */ #define PCI_DID_INTEL_APL_NB 0x5af0 @@ -4136,6 +4138,7 @@ #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 +#define PCI_DID_INTEL_RPL_P_ID_3 0xa708 /* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 |