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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-07 03:08:27 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-08 20:15:09 +0000 |
| commit | 78633e3d810119b09653320e9ad43b07d569eada (patch) | |
| tree | 8f379905bc56f3ca2479dcbc324b58c3cbef9cf7 /src/include | |
| parent | 9f5b2f75ad5c500dbe8a3d9f27e6107fd56ee76d (diff) | |
| download | coreboot-78633e3d810119b09653320e9ad43b07d569eada.tar.gz coreboot-78633e3d810119b09653320e9ad43b07d569eada.tar.bz2 coreboot-78633e3d810119b09653320e9ad43b07d569eada.zip | |
soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h
The bit position of the P state enable bit in the 8 P state MSRs is
identical for all AMD chips including the family 16h model 30h APU that
lives outside of soc/amd. The other bits in those 8 MSRs are more or
less family- and model-specific.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/amd/msr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 1fd7ec7dbc41..1c1a82579b43 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -41,6 +41,9 @@ #define PS_STS_REG 0xC0010063 #define PSTATE_0_MSR 0xC0010064 #define PSTATE_MSR(pstate) (PSTATE_0_MSR + (pstate)) +#define PSTATE_DEF_HI_ENABLE_SHIFT 31 +#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) + #define MSR_PATCH_LOADER 0xC0010020 #define MSR_COFVID_STS 0xC0010071 |