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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-06-10 10:34:20 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-26 19:10:31 +0100 |
| commit | 8adf7a2c50dcb3a7f09b66c1f3918ab195d8c5ec (patch) | |
| tree | 50f9e2599a850991df65570ccf216682f9d7b406 /src/include | |
| parent | d5686fe23b1341ca2c72b2941cf80577e6198f23 (diff) | |
| download | coreboot-8adf7a2c50dcb3a7f09b66c1f3918ab195d8c5ec.tar.gz coreboot-8adf7a2c50dcb3a7f09b66c1f3918ab195d8c5ec.tar.bz2 coreboot-8adf7a2c50dcb3a7f09b66c1f3918ab195d8c5ec.zip | |
Log device path into CMOS during probe stages
One of the most common hangs during coreboot execution
is during ramstage device init steps. Currently there
are a set of (somewhat misleading) post codes during this
phase which give some indication as to where execution
stopped, but it provides no information on what device
was actually being initialized at that point.
This uses the new CMOS "extra" log banks to store the
encoded device path of the device that is about to be
touched by coreboot. This way if the system hangs when
talking to the device there will be some indication where
to investigate next.
interrupted boot with reset button and
gathered the eventlog after several test runs:
26 | 2013-06-10 10:32:48 | System boot | 120
27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize
28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0
29 | 2013-06-10 10:32:48 | Reset Button
30 | 2013-06-10 10:32:48 | System Reset
Change-Id: I6045bd4c384358b8a4e464eb03ccad639283939c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58105
Reviewed-on: http://review.coreboot.org/4230
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/console/console.h | 5 | ||||
| -rw-r--r-- | src/include/pc80/mc146818rtc.h | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/include/console/console.h b/src/include/console/console.h index e6962cc69dd3..5750b4a52501 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -74,8 +74,13 @@ void console_tx_flush(void); void post_code(u8 value); #if CONFIG_CMOS_POST_EXTRA void post_log_extra(u32 value); +struct device; +void post_log_path(struct device *dev); +void post_log_clear(void); #else #define post_log_extra(x) do {} while (0) +#define post_log_path(x) do {} while (0) +#define post_log_clear() do {} while (0) #endif /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index b0e9f2cc0398..fd403087a666 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -217,6 +217,8 @@ static inline enum cb_err get_option(void *dest __attribute__((unused)), #define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) #define CMOS_POST_BANK_1_EXTRA (CMOS_POST_OFFSET + 7) +#define CMOS_POST_EXTRA_DEV_PATH 0x01 + void cmos_post_log(void); #endif /* CONFIG_CMOS_POST */ |