summaryrefslogtreecommitdiffstats
path: root/src/include
diff options
context:
space:
mode:
authorJulius Werner <jwerner@chromium.org>2019-06-06 17:03:44 -0700
committerJulius Werner <jwerner@chromium.org>2019-06-10 18:02:33 +0000
commit99e45ceb35ff9a4c48e516e6d005ebfae54b6591 (patch)
tree8f42f859485f2dd4a0c101e613fd607b3000f219 /src/include
parent1b7f99bd6b52e3fd03653dca80af3faf6e7e8852 (diff)
downloadcoreboot-99e45ceb35ff9a4c48e516e6d005ebfae54b6591.tar.gz
coreboot-99e45ceb35ff9a4c48e516e6d005ebfae54b6591.tar.bz2
coreboot-99e45ceb35ff9a4c48e516e6d005ebfae54b6591.zip
spi_flash: Add Dual SPI support
This patch adds support to read SPI flash in Dual SPI mode, where both MISO and MOSI lines are used for output mode (specifically Fast Read Dual Output (0x3b) where the command is still sent normally, not Fast Read Dual I/O (0xbb) whose additional benefit should be extremely marginal for our use cases but which would be more complicated to implement). This feature needs to be supported by both the flash chip and the controller, so we add a new dual_spi flag (and a new flags field to hold it) to the spi_flash structure and a new optional xfer_dual() function pointer to the spi_ctrlr structure. When both are provided, Dual SPI mode is used automatically, otherwise things work as before. This patch only adds the dual_spi flag exemplary to all Winbond and Gigadevice chips, other vendors need to be added as needed. Change-Id: Ic6808224c99af32b6c5c43054135c8f4c03c1feb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/spi-generic.h3
-rw-r--r--src/include/spi_flash.h7
2 files changed, 10 insertions, 0 deletions
diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h
index c24aadd926c7..d0f957f1f9fb 100644
--- a/src/include/spi-generic.h
+++ b/src/include/spi-generic.h
@@ -125,6 +125,7 @@ enum {
* setup: Setup given SPI device bus.
* xfer: Perform one SPI transfer operation.
* xfer_vector: Vector of SPI transfer operations.
+ * xfer_dual: (optional) Perform one SPI transfer in Dual SPI mode.
* max_xfer_size: Maximum transfer size supported by the controller
* (0 = invalid,
* SPI_CTRLR_DEFAULT_MAX_XFER_SIZE = unlimited)
@@ -145,6 +146,8 @@ struct spi_ctrlr {
size_t bytesout, void *din, size_t bytesin);
int (*xfer_vector)(const struct spi_slave *slave,
struct spi_op vectors[], size_t count);
+ int (*xfer_dual)(const struct spi_slave *slave, const void *dout,
+ size_t bytesout, void *din, size_t bytesin);
uint32_t max_xfer_size;
uint32_t flags;
int (*flash_probe)(const struct spi_slave *slave,
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index 936b0abe850d..3a0c38367688 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -90,6 +90,13 @@ struct spi_flash_ops {
struct spi_flash {
struct spi_slave spi;
u8 vendor;
+ union {
+ u8 raw;
+ struct {
+ u8 dual_spi : 1;
+ u8 _reserved : 7;
+ };
+ } flags;
u16 model;
const char *name;
u32 size;