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| author | Naresh Solanki <Naresh.Solanki@9elements.com> | 2023-08-10 13:21:44 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-12-13 14:27:09 +0000 |
| commit | 54662610197d7304b48d8e85a5b13263db3357f2 (patch) | |
| tree | 757cc0560b30e2099ee6c3892bfdf731eca5e3e1 /src/lib/bootsplash.c | |
| parent | 3e25f85d68d10249473d422c4c19dc30ea55e8b0 (diff) | |
| download | coreboot-54662610197d7304b48d8e85a5b13263db3357f2.tar.gz coreboot-54662610197d7304b48d8e85a5b13263db3357f2.tar.bz2 coreboot-54662610197d7304b48d8e85a5b13263db3357f2.zip | |
drivers/uart/pl011.c Perform basic UART init
Configure UART baud rate, Line Control register as 8n1 with FIFO
enable and enable UART TX and RX.
Change-Id: I090344a20430dc370a0b93ff7fbbae54111fae24
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/lib/bootsplash.c')
0 files changed, 0 insertions, 0 deletions