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| author | Subrata Banik <subrata.banik@intel.com> | 2019-05-06 14:17:41 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-05-12 03:10:24 +0000 |
| commit | 7e893a02c0cc04b8fdcfee0b4dc0ff790bfe40c5 (patch) | |
| tree | 37dedc9deb63d0961d241a24e08fed15b54d344a /src/lib/timestamp.c | |
| parent | 7bc9036d160c6235d96e1bed49331696d7fa9a09 (diff) | |
| download | coreboot-7e893a02c0cc04b8fdcfee0b4dc0ff790bfe40c5.tar.gz coreboot-7e893a02c0cc04b8fdcfee0b4dc0ff790bfe40c5.tar.bz2 coreboot-7e893a02c0cc04b8fdcfee0b4dc0ff790bfe40c5.zip | |
Kconfig: Create RAMPAYLOAD kconfig
This patch enables coreboot flow to skip ramstage as
individual stage to load payload. Instead it is expected
to load payload from postcar stage.
Change-Id: I839f2d34a93b69ca6bf3de6594e2ad9f66ee7135
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/lib/timestamp.c')
0 files changed, 0 insertions, 0 deletions