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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2020-03-13 17:21:59 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 12:56:09 +0000
commit4d5fd77cf82e95b74c80790389c3616de2b81411 (patch)
tree2e2130fb889cbc818cedd45022cd4b18fbf598cb /src/lib
parentcb1e386eabfbf2d0851ed58f97d11a7bab431983 (diff)
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lib/spd_bin: Cleanup spd_get_banks
Remove the switch case in spd_get_banks. The LPDDR4X adapt DDR4 attributes. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/lib')
-rw-r--r--src/lib/spd_bin.c19
1 files changed, 6 insertions, 13 deletions
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index f59e1870375e..4be00518448e 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -76,22 +76,15 @@ static int spd_get_banks(const uint8_t spd[], int dram_type)
static const int ddr3_banks[4] = { 8, 16, 32, 64 };
static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
- switch (dram_type) {
- /* DDR3 and LPDDR3_Intel have the same bank definition */
- case SPD_DRAM_DDR3:
- case SPD_DRAM_LPDDR3_INTEL:
- if (index >= ARRAY_SIZE(ddr3_banks))
- return -1;
- return ddr3_banks[index];
- /* LPDDR3, LPDDR4 and DDR4 have the same bank definition */
- case SPD_DRAM_LPDDR3_JEDEC:
- case SPD_DRAM_DDR4:
- case SPD_DRAM_LPDDR4:
+
+ if (use_ddr4_params(dram_type)) {
if (index >= ARRAY_SIZE(ddr4_banks))
return -1;
return ddr4_banks[index];
- default:
- return -1;
+ } else {
+ if (index >= ARRAY_SIZE(ddr3_banks))
+ return -1;
+ return ddr3_banks[index];
}
}