remove the code which is not ready to release.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 0 insertions, 1027 deletions

diff --git a/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl b/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl
deleted file mode 100644
index 6a1b002474a0..000000000000
--- a/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/* This file defines the processor and performance state capability
- * for each core in the system.  It is included into the DSDT for each
- * core.  It assumes that each core of the system has the same performance
- * characteristics.
-*/
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
-	{
-		Scope (\_PR) {
-		Processor(CPU0,0,0x808,0x06) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU1,1,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU2,2,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU3,3,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-	}
-*/
-	/* P-state support: The maximum number of P-states supported by the */
-	/* CPUs we'll use is 6. */
-	/* Get from AMI BIOS. */
-	Name(_PSS, Package(){
-		Package ()
-		{
-		    0x00000AF0,
-		    0x0000BF81,
-		    0x00000002,
-		    0x00000002,
-		    0x00000000,
-		    0x00000000
-		},
-
-		Package ()
-		{
-		    0x00000578,
-		    0x000076F2,
-		    0x00000002,
-		    0x00000002,
-		    0x00000001,
-		    0x00000001
-		}
-	})
-
-	Name(_PCT, Package(){
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
-	})
-
-	Method(_PPC, 0){
-		Return(0)
-	}
diff --git a/src/mainboard/amd/bimini_fam10/acpi/ide.asl b/src/mainboard/amd/bimini_fam10/acpi/ide.asl
deleted file mode 100644
index 6ea2b09f2c53..000000000000
--- a/src/mainboard/amd/bimini_fam10/acpi/ide.asl
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
-	Increment(Local0)
-	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
-	Increment(Local1)
-	Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If(And(PPCR, 0x01)) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		Or(BFFG, 0x1A, BFFG)
-
-		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
-		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x01, BFFG)
-			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
-		}
-		Else {
-			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x04, BFFG)
-			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
-		}
-		Else {
-			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, NotSerialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
-		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
-		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
-		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
-		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
-		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
-		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDMM,)
-			Or(PDCR, 0x01, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTM)
-			}
-		}
-
-		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDSM,)
-			Or(PDCR, 0x02, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTS)
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xA0, CMDA)
-			Store(0xA0, CMDB)
-			Store(0xA0, CMDC)
-
-			Or(PPMM, 0x08, POMD)
-
-			If(And(PDCR, 0x01)) {
-				Or(PDMM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTM),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xB0, CMDA)
-			Store(0xB0, CMDB)
-			Store(0xB0, CMDC)
-
-			Or(PPSM, 0x08, POMD)
-
-			If(And(PDCR, 0x02)) {
-				Or(PDSM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTS),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/bimini_fam10/acpi/routing.asl b/src/mainboard/amd/bimini_fam10/acpi/routing.asl
deleted file mode 100644
index 641b168e9ba7..000000000000
--- a/src/mainboard/amd/bimini_fam10/acpi/routing.asl
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
-		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
-		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
-		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		/* Package(){0x0004FFFF, 1, 0, 17 }, */
-		/* Package(){0x0004FFFF, 2, 0, 18 }, */
-		/* Package(){0x0004FFFF, 3, 0, 19 }, */
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, 0, 17 }, */
-		/* Package(){0x0005FFFF, 1, 0, 18 }, */
-		/* Package(){0x0005FFFF, 2, 0, 19 }, */
-		/* Package(){0x0005FFFF, 3, 0, 16 }, */
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		/* Package(){0x0006FFFF, 0, 0, 18 }, */
-		/* Package(){0x0006FFFF, 1, 0, 19 }, */
-		/* Package(){0x0006FFFF, 2, 0, 16 }, */
-		/* Package(){0x0006FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		/* Package(){0x0007FFFF, 0, 0, 19 }, */
-		/* Package(){0x0007FFFF, 1, 0, 16 }, */
-		/* Package(){0x0007FFFF, 2, 0, 17 }, */
-		/* Package(){0x0007FFFF, 3, 0, 18 }, */
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		/* Package(){0x0009FFFF, 1, 0, 16 }, */
-		/* Package(){0x0009FFFF, 2, 0, 17 }, */
-		/* Package(){0x0009FFFF, 3, 0, 18 }, */
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		/* Package(){0x000AFFFF, 1, 0, 16 }, */
-		/* Package(){0x000AFFFF, 2, 0, 17 }, */
-		/* Package(){0x000AFFFF, 3, 0, 18 }, */
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSa, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSa, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/bimini_fam10/acpi/sata.asl b/src/mainboard/amd/bimini_fam10/acpi/sata.asl
deleted file mode 100644
index b5e6fc5665ae..000000000000
--- a/src/mainboard/amd/bimini_fam10/acpi/sata.asl
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P0IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P1IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P2IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P3IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (LGreater(\_SB.P0IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P0PR)
-		}
-
-		if (\_SB.P1PR) {
-			if (LGreater(\_SB.P1IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P1PR)
-		}
-
-		if (\_SB.P2PR) {
-			if (LGreater(\_SB.P2IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P2PR)
-		}
-
-		if (\_SB.P3PR) {
-			if (LGreater(\_SB.P3IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P3PR)
-		}
-	}
-}
diff --git a/src/mainboard/amd/bimini_fam10/acpi/usb.asl b/src/mainboard/amd/bimini_fam10/acpi/usb.asl
deleted file mode 100644
index 203e0ad25afc..000000000000
--- a/src/mainboard/amd/bimini_fam10/acpi/usb.asl
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-Method(UCOC, 0) {
-	Sleep(20)
-    	Store(0x13,CMTI)
-	Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if(LEqual(GPB0,PLC0)) {
-				Not(PLC0,PLC0)
-				Store(PLC0, \_SB.PT0D)
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (LEqual(GPB1,PLC1)) {
-				Not(PLC1,PLC1)
-				Store(PLC1, \_SB.PT1D)
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (LEqual(GPB2,PLC2)) {
-				Not(PLC2,PLC2)
-				Store(PLC2, \_SB.PT2D)
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (LEqual(GPB3,PLC3)) {
-				Not(PLC3,PLC3)
-				Store(PLC3, \_SB.PT3D)
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (LEqual(GPB4,PLC4)) {
-				Not(PLC4,PLC4)
-				Store(PLC4, \_SB.PT4D)
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (LEqual(GPB5,PLC5)) {
-				Not(PLC5,PLC5)
-				Store(PLC5, \_SB.PT5D)
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (LEqual(GPB6,PLC6)) {
-				Not(PLC6,PLC6)
-				Store(PLC6, \_SB.PT6D)
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- 	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (LEqual(GPB7,PLC7)) {
-				Not(PLC7,PLC7)
-				Store(PLC7, \_SB.PT7D)
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (LEqual(G8IS,PLC8)) {
-				Not(PLC8,PLC8)
-				Store(PLC8, \_SB.PT8D)
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (LEqual(G9IS,0)) {
-			Store(1,\_SB.PT9D)
-			}
-		}
-	}
-}