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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-14 23:58:19 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-16 17:14:34 +0000 |
| commit | aef7007b0c519b48cebbb88cfc1af109031d10f4 (patch) | |
| tree | 08d61cb7defe42b97df01b282e970fcbad6babce /src/mainboard/amd/birman | |
| parent | 42f7dc7493ff09ae75ec22f0d0b291cfcead71a6 (diff) | |
| download | coreboot-aef7007b0c519b48cebbb88cfc1af109031d10f4.tar.gz coreboot-aef7007b0c519b48cebbb88cfc1af109031d10f4.tar.bz2 coreboot-aef7007b0c519b48cebbb88cfc1af109031d10f4.zip | |
mb/amd/birman/devicetree_phoenix: update USB PHY settings
Update the initial USB PHY tuning values that were a copy of the ones
from the Chausie mainboard to the values used in the Birman UEFI
firmware reference implementation. The USB3 PHY tuning values are still
the same while some of the USB2 PHY tuning values are different. The
last two USB2 PHYs that are used by the USB4 controllers have a
different parameter set compared to the other USB2 PHYs.
TEST=All USB ports on Birman function as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0ddfa2594d66b21582282ab8509c921a6e81a93f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75823
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/birman')
| -rw-r--r-- | src/mainboard/amd/birman/devicetree_phoenix.cb | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index 6cbb36fd2491..689476498f64 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -44,13 +44,13 @@ chip soc/amd/phoenix register "usb_phy_custom" = "1" register "usb_phy" = "{ .Usb2PhyPort[0] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -58,13 +58,13 @@ chip soc/amd/phoenix .txrestune = 0x2, }, .Usb2PhyPort[1] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -72,13 +72,13 @@ chip soc/amd/phoenix .txrestune = 0x2, }, .Usb2PhyPort[2] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -86,13 +86,13 @@ chip soc/amd/phoenix .txrestune = 0x2, }, .Usb2PhyPort[3] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -100,13 +100,13 @@ chip soc/amd/phoenix .txrestune = 0x2, }, .Usb2PhyPort[4] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -114,13 +114,13 @@ chip soc/amd/phoenix .txrestune = 0x2, }, .Usb2PhyPort[5] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -131,13 +131,13 @@ chip soc/amd/phoenix .compdistune = 0x3, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, - .txvreftune = 0x3, + .txvreftune = 0x6, .txhsxvtune = 0x3, .txrestune = 0x2, }, @@ -145,13 +145,13 @@ chip soc/amd/phoenix .compdistune = 0x3, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, - .txvreftune = 0x3, + .txvreftune = 0x6, .txhsxvtune = 0x3, .txrestune = 0x2, }, |