mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK

Warning: not tested on hardware.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38867
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 29 insertions, 0 deletions

diff --git a/src/mainboard/amd/olivehill/bootblock.c b/src/mainboard/amd/olivehill/bootblock.c
new file mode 100644
index 000000000000..d1f8d606e40f
--- /dev/null
+++ b/src/mainboard/amd/olivehill/bootblock.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <amdblocks/acpimmio.h>
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	int i;
+	u32 val;
+
+	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
+	pm_write8(0xea, 0x1);
+
+	/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
+	for (i = 0; i < 200000; i++)
+		val = inb(0xcd6);
+}