diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-10-14 17:48:22 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-15 16:53:19 +0000 |
| commit | f0d62cefe855017a9e3f47aa3b0fc187ef8a5931 (patch) | |
| tree | c7c12feb32e8d439da668f943c85bf29c9c41249 /src/mainboard/amd/pademelon/OemCustomize.c | |
| parent | 68eb439d80919d54247114c8c6035a65a97eadc8 (diff) | |
| download | coreboot-f0d62cefe855017a9e3f47aa3b0fc187ef8a5931.tar.gz coreboot-f0d62cefe855017a9e3f47aa3b0fc187ef8a5931.tar.bz2 coreboot-f0d62cefe855017a9e3f47aa3b0fc187ef8a5931.zip | |
mb/amd/padmelon: rename to pademelon
This AMD reference board is called Pademelon and not Padmelon, so fix
the name in coreboot. Also update the corresponding documentation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/amd/pademelon/OemCustomize.c')
| -rw-r--r-- | src/mainboard/amd/pademelon/OemCustomize.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/mainboard/amd/pademelon/OemCustomize.c b/src/mainboard/amd/pademelon/OemCustomize.c new file mode 100644 index 000000000000..e65f750cd58d --- /dev/null +++ b/src/mainboard/amd/pademelon/OemCustomize.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/amd/stoneyridge/chip.h> +#include <amdblocks/agesawrapper.h> + +#define DIMMS_PER_CHANNEL 1 +#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH +#error "Too many DIMM sockets defined for the mainboard" +#endif + +static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_A, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_B, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), + MOTHER_BOARD_LAYERS(LAYERS_6), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x08, 0x04, + 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x05, 0x0A, 0x00, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x00, 0x02, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x04, 0x02, 0x08), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x04, 0x08, 0x00, + 0x00, 0x00, 0x00), + PSO_END +}; + +void OemPostParams(AMD_POST_PARAMS *PostParams) +{ + PostParams->MemConfig.PlatformMemoryConfiguration = + (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; + PostParams->MemConfig.CfgUmaAbove4G = TRUE; +} |