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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-10-14 17:48:22 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-15 16:53:19 +0000 |
| commit | f0d62cefe855017a9e3f47aa3b0fc187ef8a5931 (patch) | |
| tree | c7c12feb32e8d439da668f943c85bf29c9c41249 /src/mainboard/amd/pademelon/devicetree.cb | |
| parent | 68eb439d80919d54247114c8c6035a65a97eadc8 (diff) | |
| download | coreboot-f0d62cefe855017a9e3f47aa3b0fc187ef8a5931.tar.gz coreboot-f0d62cefe855017a9e3f47aa3b0fc187ef8a5931.tar.bz2 coreboot-f0d62cefe855017a9e3f47aa3b0fc187ef8a5931.zip | |
mb/amd/padmelon: rename to pademelon
This AMD reference board is called Pademelon and not Padmelon, so fix
the name in coreboot. Also update the corresponding documentation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/amd/pademelon/devicetree.cb')
| -rw-r--r-- | src/mainboard/amd/pademelon/devicetree.cb | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/amd/pademelon/devicetree.cb b/src/mainboard/amd/pademelon/devicetree.cb new file mode 100644 index 000000000000..a0ba7255bcbd --- /dev/null +++ b/src/mainboard/amd/pademelon/devicetree.cb @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/stoneyridge + register "uma_mode" = "UMAMODE_AUTO_LEGACY" + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device ref iommu on end + device ref gfx on end + device ref gfx_hda on end + device ref gpp_bridge_1 on end # mini PCIe slot x1 + device ref gpp_bridge_3 on end # LAN RTL8111F + device ref gpp_bridge_4 on end # LAN RTL8111F + device ref hda_bridge on end + device ref hda on end + device ref xhci on end + device ref sata on end + device ref ehci on end + device ref lpc_bridge on + chip superio/fintek/f81803a + device pnp 4e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.4 on # HWM + io 0x60 = 0x220 + irq 0x70 = 0 + end + device pnp 4e.5 off end # KBC + device pnp 4e.6 off end # GPIO + device pnp 4e.7 off end # WDT + device pnp 4e.a off end # PME + end # f81803a + end + device ref sdhci on end + end #domain +end #soc/amd/stoneyridge |