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| author | efdesign98 <efdesign98@gmail.com> | 2011-06-20 17:38:49 -0700 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-06-22 01:27:46 +0200 |
| commit | 05a89ab922473f375820a3bd68691bb085c62448 (patch) | |
| tree | 22510d53ab35d80987cb17f2a11ce08039db49a5 /src/mainboard/amd/persimmon/devicetree.cb | |
| parent | ee39ea7e7edf9699f1bae1b2708ad6816f054817 (diff) | |
| download | coreboot-05a89ab922473f375820a3bd68691bb085c62448.tar.gz coreboot-05a89ab922473f375820a3bd68691bb085c62448.tar.bz2 coreboot-05a89ab922473f375820a3bd68691bb085c62448.zip | |
Rename {CPU|NB|SB}/amd/*_wrapper folders
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.
Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/amd/persimmon/devicetree.cb')
| -rw-r--r-- | src/mainboard/amd/persimmon/devicetree.cb | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 3a9ec400a63f..a6763884c71e 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -16,17 +16,17 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -chip northbridge/amd/agesa_wrapper/family14/root_complex +chip northbridge/amd/agesa/family14/root_complex device lapic_cluster 0 on - chip cpu/amd/agesa_wrapper/family14 + chip cpu/amd/agesa/family14 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex + chip northbridge/amd/agesa/family14 # CPU side of HT root complex # device pci 18.0 on # northbridge - chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex + chip northbridge/amd/agesa/family14 # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 device pci 1.1 on end # Internal Multimedia @@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex device pci 6.0 off end # PCIE P2P bridge 0x9606 device pci 7.0 off end # PCIE P2P bridge 0x9607 device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa_wrapper northbridge + end # agesa northbridge - chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.1 on end # USB @@ -89,7 +89,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex device pci 15.3 off end # PCIe PortD register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx_wrapper/sb800 + end #southbridge/amd/cimx/sb800 # end # device pci 18.0 # These seem unnecessary device pci 18.0 on end @@ -101,7 +101,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex device pci 18.5 on end device pci 18.6 on end device pci 18.7 on end - end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #pci_domain -end #northbridge/amd/agesa_wrapper/family14/root_complex +end #northbridge/amd/agesa/family14/root_complex |