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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-13 10:03:31 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-19 08:17:06 +0000 |
| commit | 0ce41f1a116a816e774ebbd1130d27d7ee70e7e9 (patch) | |
| tree | 983a793e01bbf09ed1e9c74534d4b78f9d3f2866 /src/mainboard/amd | |
| parent | 16f9bf83e00c786275d3fcc9d512d145ef6c93c9 (diff) | |
| download | coreboot-0ce41f1a116a816e774ebbd1130d27d7ee70e7e9.tar.gz coreboot-0ce41f1a116a816e774ebbd1130d27d7ee70e7e9.tar.bz2 coreboot-0ce41f1a116a816e774ebbd1130d27d7ee70e7e9.zip | |
src: Add required space after "switch"
Change-Id: I85cf93e30606bc7838852bd300a369e79370629a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/amd')
5 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index c995cff5c8a6..b6267a69bb2b 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -91,7 +91,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - switch(MemData->ParameterListPtr->DDR3Voltage){ + switch (MemData->ParameterListPtr->DDR3Voltage) { case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~(UINT8)BIT6; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 9f273a4d8bd1..03b849d0d08e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -150,7 +150,7 @@ unsigned long mainboard_write_acpi_tables(struct device *device, current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); /* pci0 and pci1 are in dsdt */ ssdtx = (acpi_header_t *)current; - switch(sysconf.hcid[i]) { + switch (sysconf.hcid[i]) { case 1: file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index adf43c015719..4e84fb2062ae 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -151,7 +151,7 @@ void get_bus_conf(void) /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); - switch(sysconf.hcid[i]) { + switch (sysconf.hcid[i]) { case 1: /* 8132 */ case 3: /* 8131 */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index d9596dad0700..fb9473f008b8 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) if (!(sysconf.pci1234[i] & 0x1)) continue; - switch(sysconf.hcid[i]) { + switch (sysconf.hcid[i]) { case 1: case 3: dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); @@ -137,7 +137,7 @@ static void *smp_write_config_table(void *v) int jj; struct device *dev; struct resource *res; - switch(sysconf.hcid[i]) { + switch (sysconf.hcid[i]) { case 1: case 3: dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 56c48c8a8d65..e7b0e2958442 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -63,7 +63,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch(MemData->ParameterListPtr->DDR3Voltage){ + switch (MemData->ParameterListPtr->DDR3Voltage) { case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~(UINT8)BIT6; |