diff options
| author | Anand Vaikar <a.vaikar2021@gmail.com> | 2023-04-12 12:09:37 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-10 12:29:29 +0000 |
| commit | 20d658e53ca8694dedd5bfbdc70ce384feeea815 (patch) | |
| tree | f86e6d145bfdc4b3ea29c4514f78a28c4bfed110 /src/mainboard/amd | |
| parent | 383c4e7530087061805130a4d62b4f0dee73281a (diff) | |
| download | coreboot-20d658e53ca8694dedd5bfbdc70ce384feeea815.tar.gz coreboot-20d658e53ca8694dedd5bfbdc70ce384feeea815.tar.bz2 coreboot-20d658e53ca8694dedd5bfbdc70ce384feeea815.zip | |
mb/amd/mayan: Enable MXM PCIe slot
Follow the EC GPIO programming sequence to enable the MXM PCIe slot.
Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/mayan/devicetree_phoenix.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/amd/mayan/ec.c | 19 |
2 files changed, 19 insertions, 1 deletions
diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 697db12f9f7b..ac219dc7f470 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -158,6 +158,7 @@ chip soc/amd/phoenix device domain 0 on device ref iommu on end + device ref gpp_bridge_1_1 on end # MXM device ref gpp_bridge_2_1 on end # GBE device ref gpp_bridge_2_2 on end # WIFI device ref gpp_bridge_2_4 on end # NVMe SSD diff --git a/src/mainboard/amd/mayan/ec.c b/src/mainboard/amd/mayan/ec.c index 1b1d09bc7287..d60814fe9adc 100644 --- a/src/mainboard/amd/mayan/ec.c +++ b/src/mainboard/amd/mayan/ec.c @@ -8,7 +8,14 @@ #define MAYAN_EC_CMD 0x666 #define MAYAN_EC_DATA 0x662 +#define EC_GPIO_1_ADDR 0xA1 +#define EC_GPIO_EVAL_PWREN BIT(1) + +#define EC_GPIO_2_ADDR 0xA2 +#define EC_GPIO_EVAL_SLOT_PWR BIT(5) + #define EC_GPIO_3_ADDR 0xA3 +#define EC_GPIO_EVAL_RST_AUX BIT(0) #define EC_GPIO_LOM_RESET_AUX BIT(1) #define EC_GPIO_7_ADDR 0xA7 @@ -35,8 +42,18 @@ static void configure_ec_gpio(void) { uint8_t tmp; + /* Enable MXM slot: set EC_GPIO_EVAL_PWREN, EC_GPIO_EVAL_SLOT_PWR + and EC_GPIO_EVAL_RST_AUX */ + tmp = ec_read(EC_GPIO_1_ADDR); + tmp |= EC_GPIO_EVAL_PWREN; + ec_write(EC_GPIO_1_ADDR, tmp); + + tmp = ec_read(EC_GPIO_2_ADDR); + tmp |= EC_GPIO_EVAL_SLOT_PWR; + ec_write(EC_GPIO_2_ADDR, tmp); + tmp = ec_read(EC_GPIO_3_ADDR); - tmp |= EC_GPIO_LOM_RESET_AUX; + tmp |= EC_GPIO_LOM_RESET_AUX | EC_GPIO_EVAL_RST_AUX; ec_write(EC_GPIO_3_ADDR, tmp); tmp = ec_read(EC_GPIO_7_ADDR); |