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authorMarc Jones <marcj303@gmail.com>2017-09-19 14:15:29 -0600
committerMartin Roth <martinroth@google.com>2017-09-21 17:31:10 +0000
commitcd935e678a8b12cae0827c438a9c86489e6acee3 (patch)
tree76a09fdaaa0798696ba23ab7e6a04dc1a17bcc62 /src/mainboard/amd
parent229e021110e40f603bb12b634c4b91923ef02727 (diff)
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amd/gardenia: Fix number of memory channels
Gardenia (with Stoney Processor) has a single memory channel, not two. This corrects DMI type 17 reporting and the memory clear functions. Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21602 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/gardenia/OemCustomize.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c
index 3893e5dbcb0e..6ca84b4b86da 100644
--- a/src/mainboard/amd/gardenia/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/OemCustomize.c
@@ -21,7 +21,7 @@
static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),