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| author | Fred Reitberger <reitbergerfred@gmail.com> | 2023-03-28 16:06:57 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-30 19:55:15 +0000 |
| commit | d8707e7e0f10f8ff265a0cd515d888333bf852c5 (patch) | |
| tree | e3ed1b7667ed69b517a746aff96fabbc610c73c7 /src/mainboard/amd | |
| parent | b607c6d5840629f200727180d71454e144ba3a42 (diff) | |
| download | coreboot-d8707e7e0f10f8ff265a0cd515d888333bf852c5.tar.gz coreboot-d8707e7e0f10f8ff265a0cd515d888333bf852c5.tar.bz2 coreboot-d8707e7e0f10f8ff265a0cd515d888333bf852c5.zip | |
mb/amd/birman/early_gpio: Add M2 SSD resets
Add early configuration of the GPIOs that control the M2 SSD resets.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I81439d193bdd7296d8a8fea83c5c6be2c75adbea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73989
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/birman/early_gpio.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/amd/birman/early_gpio.c b/src/mainboard/amd/birman/early_gpio.c index 9089f6ab044c..4915996881ba 100644 --- a/src/mainboard/amd/birman/early_gpio.c +++ b/src/mainboard/amd/birman/early_gpio.c @@ -36,6 +36,10 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), /* PCIE_RST1_L */ PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* M2_SSD0_RST_L */ + PAD_GPO(GPIO_78, HIGH), + /* M2_SSD1_RST_L */ + PAD_GPO(GPIO_79, HIGH), /* Enable UART 2 */ /* UART2_RXD */ |