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| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-06-09 11:04:37 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-10 15:21:57 +0000 |
| commit | f089f9b8c6fd72c068178bb2c94d0f96008c4612 (patch) | |
| tree | f589ff4689f4032a9d39ea87df8c9d11cc476fb0 /src/mainboard/amd | |
| parent | f9b5665d280faa35c6b41fe0c48a9e9e1afd634b (diff) | |
| download | coreboot-f089f9b8c6fd72c068178bb2c94d0f96008c4612.tar.gz coreboot-f089f9b8c6fd72c068178bb2c94d0f96008c4612.tar.bz2 coreboot-f089f9b8c6fd72c068178bb2c94d0f96008c4612.zip | |
mb/chausie/ec: Set MS bit in SW02
Set the MS bit in EC SW02 register to enable s0i3
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I97b6adf48b49635251c70015f1d87fd8ca11d539
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/chausie/ec.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/amd/chausie/ec.c b/src/mainboard/amd/chausie/ec.c index ac484b217406..a2ed4ed5b4ac 100644 --- a/src/mainboard/amd/chausie/ec.c +++ b/src/mainboard/amd/chausie/ec.c @@ -26,6 +26,9 @@ #define EC_GPIO_MP2_SEL (1 << 2) #define EC_GPIO_WWAN_N_LOM_SW (1 << 3) +#define EC_SW02_ADDR 0xB7 +#define EC_SW02_MS (1 << 7) + static void configure_ec_gpio(void) { uint8_t tmp; @@ -49,6 +52,10 @@ static void configure_ec_gpio(void) tmp = ec_read(EC_GPIO_C_ADDR); tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW; ec_write(EC_GPIO_C_ADDR, tmp); + + tmp = ec_read(EC_SW02_ADDR); + tmp |= EC_SW02_MS; + ec_write(EC_SW02_ADDR, tmp); } void chausie_ec_init(void) |