mb/amd/db-ft3b-lc: Drop unmaintained ROMCC board

Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: Ib4a95c650cc4d1cddc2ba530c12ce448a1943b34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

23 files changed, 0 insertions, 2002 deletions

diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
deleted file mode 100644
index ebdea429904c..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *               2013 - 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <device/azalia.h>
-#include <FchPlatform.h>
-#include <stdlib.h>
-
-#include "imc.h"
-#include "hudson.h"
-
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_READ_SPD,                 agesa_ReadSpd_from_cbfs },
-	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config },
-	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/**
- * Realtek ALC272 CODEC Verb Table
- */
-static const CODEC_ENTRY Alc272_VerbTbl[] = {
-	{ 0x11, 0x411111F0 },               /*        - S/PDIF Output 2         */
-	{ 0x12, 0x411111F0 },               /*        - Digital Mic 1/2 [GPIO0] */
-	{ 0x13, 0x411111F0 },               /*        - Digital Mic 3/4 [GPIO1] */
-	{ 0x14, 0x411111F0 },               /* Port D - Front Panel headphone   */
-	{ 0x15, 0x411111F0 },               /* Port A - Surround                */
-	{ 0x17, 0x411111F0 },               /* Port H - Mono                    */
-	{ 0x18,                             /* Port B - MIC - combo jack        */
-			(AZALIA_PINCFG_PORT_JACK << 30)
-			| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
-			| (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
-			| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
-			| (AZALIA_PINCFG_COLOR_BLACK << 12)
-			| (4 << 4)
-			| (0 << 0)
-	},
-	{ 0x19, 0x411111F0 },               /* Port F - Front Panel Mic        */
-	{ 0x1A, 0x411111F0 },               /* Port C - LINE1      */
-	{ 0x1B, 0x411111F0 },               /* Port E - Front Panel line-out   */
-	{ 0x1D, 0x40130605 },               /*        - PCBEEP     */
-	{ 0x1E, 0x411111F0 },               /*        - SPDIF_OUT1 */
-	{ 0x21,                             /* Port I - HPout - combo jack     */
-			(AZALIA_PINCFG_PORT_JACK << 30)
-			| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
-			| (AZALIA_PINCFG_DEVICE_HP_OUT << 20)
-			| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
-			| (AZALIA_PINCFG_COLOR_BLACK << 12)
-			| (4 << 4)
-			| (0 << 0)
-	},
-	{ 0xFF, 0xFFFFFFFF },
-};
-
-static const CODEC_TBL_LIST CodecTableList[] =
-{
-	{0x10ec0272, Alc272_VerbTbl},
-	{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
-};
-
-#define FAN_INPUT_INTERNAL_DIODE	0
-#define FAN_INPUT_TEMP0			1
-#define FAN_INPUT_TEMP1			2
-#define FAN_INPUT_TEMP2			3
-#define FAN_INPUT_TEMP3			4
-#define FAN_INPUT_TEMP0_FILTER		5
-#define FAN_INPUT_ZERO			6
-#define FAN_INPUT_DISABLED		7
-
-#define FAN_AUTOMODE			(1 << 0)
-#define FAN_LINEARMODE			(1 << 1)
-#define FAN_STEPMODE			~(1 << 1)
-#define FAN_POLARITY_HIGH		(1 << 2)
-#define FAN_POLARITY_LOW		~(1 << 2)
-
-/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
-#define FREQ_28KHZ			0x0
-#define FREQ_25KHZ			0x1
-#define FREQ_23KHZ			0x2
-#define FREQ_21KHZ			0x3
-#define FREQ_29KHZ			0x4
-#define FREQ_18KHZ			0x5
-#define FREQ_100HZ			0xF7
-#define FREQ_87HZ			0xF8
-#define FREQ_58HZ			0xF9
-#define FREQ_44HZ			0xFA
-#define FREQ_35HZ			0xFB
-#define FREQ_29HZ			0xFC
-#define FREQ_22HZ			0xFD
-#define FREQ_14HZ			0xFE
-#define FREQ_11HZ			0xFF
-
-/*
- * Hardware Monitor Fan Control
- * Hardware limitation:
- *  HWM will fail to read the input temperature via I2C if other
- *  software switches the I2C address.  AMD recommends using IMC
- *  to control fans, instead of HWM.
- */
-static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
-{
-	FCH_HWM_FAN_CTR oem_factl[5] = {
-		/*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */
-		/* DB-FT3 FanOUT0 Fan header J32 */
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		/* DB-FT3 FanOUT1 Fan header J31*/
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-	};
-	LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
-
-	/* Enable IMC fan control. the recommended way */
-	if (CONFIG(HUDSON_IMC_FWM)) {
-		/* HwMonitorEnable = TRUE &&  HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
-		FchParams->Hwm.HwMonitorEnable = TRUE;
-		FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;               /* 0 disable, 1 enable TSI Auto Polling */
-
-		FchParams->Imc.ImcEnable = TRUE;
-		FchParams->Hwm.HwmControl = 1;                          /* 1 IMC, 0 HWM */
-		FchParams->Imc.ImcEnableOverWrite = 1;                  /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
-
-		LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
-
-		/* Thermal Zone Parameter */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00;    /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;    /* 6 | BIT3 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98;    /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0;
-
-		/* IMC Fan Policy temperature thresholds */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;       /* AC0 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0;       /* AC1 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0;       /* AC2 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0;       /* AC3 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0;       /* AC4 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0;       /* AC5 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0;       /* AC6 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0;       /* AC7 lowest threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0;       /* critical threshold* in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
-
-		/* IMC Fan Policy PWM Settings */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0;       /* AL0 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0;       /* AL1 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0;       /* AL2 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00;    /* AL3 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00;    /* AL4 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00;    /* AL5 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00;    /* AL6 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00;    /* AL7 percentage */
-
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;    /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90;    /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
-
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60;      /* AC0 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40;      /* AC1 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0;       /* AC2 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0;       /* AC3 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0;       /* AC4 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0;       /* AC5 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0;       /* AC6 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0;       /* AC7 lowest threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0;       /* critical threshold* in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
-
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0;       /* AL0 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0;       /* AL1 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0;       /* AL2 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00;    /* AL3 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00;    /* AL4 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00;    /* AL5 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00;    /* AL6 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00;    /* AL7 percentage */
-
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2;     /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;     /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98;    /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0;
-
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3;     /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;     /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0;     /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
-
-		/* IMC Function */
-		FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;    /*BIT0 | BIT4 |BIT8; */
-
-		/* NOTE:
-		 * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
-		 * AGESA put EcDefaultMessage as global data in ROM, so we can't override it.
-		 * so we remove it from AGESA code. Please See FchInitLateHwm.
-		 */
-	} else {
-		/* HWM fan control, using the alternative method */
-		FchParams->Imc.ImcEnable = FALSE;
-		FchParams->Hwm.HwMonitorEnable = TRUE;
-		FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;                /* 1 enable, 0 disable TSI Auto Polling */
-	}
-}
-
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such Azalia, SATA, IMC etc.
- */
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
-{
-	AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams =  (FCH_RESET_DATA_BLOCK *) FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-		FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
-		FchParams->FchReset.SataEnable = hudson_sata_enable();
-		FchParams->FchReset.IdeEnable = hudson_ide_enable();
-		FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams->FchReset.Xhci1Enable = FALSE;
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
-		FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
-		/* Azalia Controller OEM Codec Table Pointer */
-		FchParams->Azalia.AzaliaPinCfg = TRUE;
-		FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){
-			.AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03,
-			.AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03,
-			.AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03,
-			.AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03
-		};
-		FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList;
-		/* Azalia Controller Front Panel OEM Table Pointer */
-
-		/* Fan Control */
-		oem_fan_control(FchParams);
-
-		/* XHCI configuration */
-		FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams->Usb.Xhci1Enable = FALSE;
-
-		/* sata configuration */
-		FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
-		switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
-		case SataRaid:
-		case SataAhci:
-		case SataAhci7804:
-		case SataLegacyIde:
-			FchParams->Sata.SataIdeMode = FALSE;
-			break;
-		case SataIde2Ahci:
-		case SataIde2Ahci7804:
-		default: /* SataNativeIde */
-			FchParams->Sata.SataIdeMode = TRUE;
-			break;
-		}
-	}
-	printk(BIOS_DEBUG, "Done\n");
-
-	return AGESA_SUCCESS;
-}
diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig
deleted file mode 100644
index f17d2d34e9fe..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/Kconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki@gmail.com>
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config BOARD_AMD_DB_FT3B_LC
-	def_bool n
-
-if BOARD_AMD_DB_FT3B_LC
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	#select BINARYPI_LEGACY_WRAPPER
-	#select ROMCC_BOOTBLOCK
-	select CPU_AMD_PI_00730F01
-	select NORTHBRIDGE_AMD_PI_00730F01
-	select SOUTHBRIDGE_AMD_PI_AVALON
-	select DEFAULT_POST_ON_LPC
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_8192
-	select GFXUMA
-
-config MAINBOARD_DIR
-	string
-	default "amd/db-ft3b-lc"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "DB-FT3b-LC"
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config HUDSON_LEGACY_FREE
-	bool
-	default y
-
-config DIMM_SPD_SIZE
-	int
-	default 128
-
-endif # BOARD_AMD_DB_FT3B_LC
diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig.name b/src/mainboard/amd/db-ft3b-lc/Kconfig.name
deleted file mode 100644
index 3197a706946c..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/Kconfig.name
+++ /dev/null
@@ -1,3 +0,0 @@
-# Disabled
-#config BOARD_AMD_DB_FT3B_LC
-#	bool "DB-FT3b-LC"
diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
deleted file mode 100644
index 97c761fa453e..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-
-## DIMM SPD for on-board memory
-SPD_BIN = $(obj)/spd.bin
-
-# Order of names in SPD_SOURCES is important!
-SPD_SOURCES  = Memphis_MEM4G16D3EABG
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
-	for f in $+; \
-	  do for c in $$(cat $$f | grep -v ^#); \
-	    do printf $$(printf '\%o' 0x$$c); \
-	  done; \
-	done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex b/src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex
deleted file mode 100644
index 3bbe027a88a0..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex
+++ /dev/null
@@ -1,237 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-# LOWCOST board has 2GB using 4 Memphis MEM4G16D3EABG chips
-
-# The datasheet is available at:
-# http://www.memphis.ag/fileadmin/datasheets/MEM4G16D3EABG_10.pdf
-
-#      SPD contents for LC (LowCost) 4GB DDR3 (1600MHz) soldered down
-
-#      0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-#              bits[3:0]: 1 = 128 SPD Bytes Used
-#              bits[6:4]: 1 = 256 SPD Bytes Total
-#              bit7     : 0 = CRC covers bytes 0 ~ 125
-11
-
-#      1 SPD Revision -
-#              0x10 = Revision 1.0
-10
-
-#      2 Key Byte / DRAM Device Type
-#              bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-#      3 Key Byte / Module Type
-#              bits[3:0]: 1 = RDIMM
-#              bits[3:0]: 2 = UDIMM
-#              bits[3:0]: 3 = SO-DIMM
-#              bits[7:4]:     reserved
-03
-
-#      4 SDRAM CHIP Density and Banks
-#              bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
-#              bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
-#              bits[6:4]: 0 = 3 (8 banks)
-#              bit7     :     reserved
-04
-
-#      5 SDRAM Addressing
-#              bits[2:0]: 1 = 10 Column Address Bits
-#              bits[5:3]: 2 = 14 Row Address Bits
-#              bits[5:3]: 3 = 15 Row Address Bits
-#              bits[7:6]:     reserved
-19
-
-#      6 Module Nominal Voltage, VDD
-#              bit0     : 0 = 1.5 V operable
-#              bit1     : 0 = NOT 1.35 V operable
-#              bit2     : 0 = NOT 1.25 V operable
-#              bits[7:3]:     reserved
-00
-
-#      7 Module Organization
-#              bits[2:0]: 2 = 16 bits
-#              bits[5:3]: 0 = 1 Rank
-#              bits[7:6]:     reserved
-02
-
-#      8 Module Memory Bus Width
-#              bits[2:0]: 3 = Primary bus width is 64 bits
-#              bits[4:3]: 0 = 0 bits (no bus width extension)
-#              bits[7:5]:     reserved
-03
-
-#      9 Fine Timebase (FTB) Dividend / Divisor
-#              bits[3:0]: 0x02 divisor
-#              bits[7:4]: 0x05 dividend
-#              5/2 = 2.5ps
-52
-
-#      10 Medium Timebase (MTB) Dividend
-#      11 Medium Timebase (MTB) Divisor
-#              1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz
-01 08
-
-#      12 SDRAM Minimum Cycle Time (tCKmin)
-#              0x0a  = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
-0A
-
-#      13 Reserved
-00
-
-#      14 CAS Latencies Supported, Least Significant Byte
-#      15 CAS Latencies Supported, Most Significant Byte
-#              Cas Latencies of 11 - 5 are supported
-FE 00
-
-#      16 Minimum CAS Latency Time (tAAmin)
-#              0x6E = 13.75ns - DDR3-1600K
-6E
-
-#      17 Minimum Write Recovery Time (tWRmin)
-#              0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-#      18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-#              0x6E = 13.75ns -  DDR3-1600K
-6E
-
-#      19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-#              0x3C = 7.5ns
-3C
-
-#      20 Minimum Row Precharge Delay Time (tRPmin)
-#              0x6E = 13.75ns -  DDR3-1600K
-6E
-
-#      21 Upper Nibbles for tRAS and tRC
-#              bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-#              bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-#      22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-#              0x118 = 35ns - DDR3-1600 (see byte 21)
-2C
-
-#      23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-#              0x186 = 48.75ns - DDR3-1600K
-95
-
-#      24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-#      25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-#              0x500 = 160ns - for 2 Gigabit chips
-#              0x820 = 260ns - for 4 Gigabit chips
-20 08
-
-#      26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-#              0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-#      27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-#              0x3c =  7.5ns -  All DDR3 SDRAM speed bins
-3C
-
-#      28 Upper Nibble for tFAWmin
-#      29 Minimum Four Activate Window Delay Time (tFAWmin)
-#              0x0140 = 40ns -  DDR3-1600, 2 KB page size
-#              0x00F0 = 30ns -  DDR3-1600, 2 KB page size
-00 F0
-
-#      30 SDRAM Optional Feature
-#              bit0     : 1= RZQ/6 supported
-#              bit1     : 1 = RZQ/7 supported
-#              bits[6:2]:     reserved
-#              bit7     : 1 = DLL Off mode supported
-83
-
-#      31 SDRAM Thermal and Refresh Options
-#              bit0     : 1 = Temp up to 95c supported
-#              bit1     : 0 = 85-95c uses 2x refresh rate
-#              bit2     : 1 = Auto Self Refresh supported
-#              bit3     : 0 = no on die thermal sensor
-#              bits[6:4]:     reserved
-#              bit7     : 0 = partial self refresh supported
-05
-
-#      32 Module Thermal Sensor
-#              0 = Thermal sensor not incorporated onto this assembly
-00
-
-#      33 SDRAM Device Type
-#              bits[1:0]: 0 = Signal Loading not specified
-#              bits[3:2]:     reserved
-#              bits[6:4]: 0 = Die count not specified
-#              bit7     : 0 = Standard Monolithic DRAM Device
-00
-
-#      34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-#      35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-#      36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-#      37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-#      38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00 00 00 00 00
-
-#      39 - 59 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-#      60 Raw Card Extension, Module Nominal Height
-#              bits[4:0]: 0 = <= 15mm tall
-#              bits[7:5]: 0 = raw card revision 0-3
-00
-
-#      61 Module Maximum Thickness
-#              bits[3:0]: 0 = thickness front <= 1mm
-#              bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-#      62 Reference Raw Card Used
-#              bits[4:0]: 0 = Reference Raw card A used
-#              bits[6:5]: 0 = revision 0
-#              bit7     : 0 = Reference raw cards A through AL
-00
-
-#      63 Address Mapping from Edge Connector to DRAM
-#              bit0     : 0 = standard mapping (not mirrored)
-#              bits[7:1]:     reserved
-00
-
-#      64 - 116 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-#      117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-#              0x0001 = AMD
-00 01
-
-#      119 Module ID: Module Manufacturing Location - oem specified
-#      120 Module ID: Module Manufacture Year in BCD
-#              0x14 = 2014
-00 14
-
-#      121 Module ID: Module Manufacture week
-#              0x12 = 12th week
-12
-
-#      122 - 125: Module Serial Number
-00 00 00 00
-
-#      126 - 127: Cyclical Redundancy Code
-00 00
diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
deleted file mode 100644
index e90b92802a4d..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x01, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x02, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x03, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x04, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x05, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* DP0 to HDMI0/DP */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID
-OemCustomizeInitEarly (
-	IN  OUT AMD_EARLY_PARAMS    *InitEarly
-	)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-}
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = {
-  /*
-   * The following macros are supported (use comma to separate macros):
-   *
-   * MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
-   *      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
-   *      AGESA will base on this value to disable unused MemClk to save power.
-   *      Example:
-   *      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
-   *           Bit AM3/S1g3 pin name
-   *           0   M[B,A]_CLK_H/L[0]
-   *           1   M[B,A]_CLK_H/L[1]
-   *           2   M[B,A]_CLK_H/L[2]
-   *           3   M[B,A]_CLK_H/L[3]
-   *           4   M[B,A]_CLK_H/L[4]
-   *           5   M[B,A]_CLK_H/L[5]
-   *           6   M[B,A]_CLK_H/L[6]
-   *           7   M[B,A]_CLK_H/L[7]
-   *      And platform has the following routing:
-   *           CS0   M[B,A]_CLK_H/L[4]
-   *           CS1   M[B,A]_CLK_H/L[2]
-   *           CS2   M[B,A]_CLK_H/L[3]
-   *           CS3   M[B,A]_CLK_H/L[5]
-   *      Then platform can specify the following macro:
-   *      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
-   *
-   * CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
-   *      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
-   *      AGESA will base on this value to tristate unused CKE to save power.
-   *
-   * ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
-   *      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
-   *      AGESA will base on this value to tristate unused ODT pins to save power.
-   *
-   * CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
-   *      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
-   *      AGESA will base on this value to tristate unused Chip select to save power.
-   *
-   * NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
-   *      Specifies the number of DIMM slots per channel.
-   *
-   * NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
-   *      Specifies the number of Chip selects per channel.
-   *
-   * NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
-   *      Specifies the number of channels per socket.
-   *
-   * OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
-   *      Specifies DDR bus speed of channel ChannelID on socket SocketID.
-   *
-   * DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
-   *      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
-   *
-   * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-   *      Byte6Seed, Byte7Seed, ByteEccSeed)
-   *      Specifies the write leveling seed for a channel of a socket.
-   *
-   * HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-   *      Byte6Seed, Byte7Seed, ByteEccSeed)
-   *      Speicifes the HW RXEN training seed for a channel of a socket
-   */
-
-#define SEED_WL 0x0E
-WRITE_LEVELING_SEED(
-       ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
-       SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
-       SEED_WL),
-
-#define SEED_A 0x12
-HW_RXEN_SEED(
-       ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
-       SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
-       SEED_A),
-
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-  MOTHER_BOARD_LAYERS(LAYERS_6),
-
-  MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-  CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
-  ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
-  CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
-
-  PSO_END
-};
-
-void OemPostParams(AMD_POST_PARAMS *PostParams)
-{
-	/* Add the memory configuration table needed for soldered down memory */
-	PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryConfiguration;
-}
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl
deleted file mode 100644
index 87b0d2169da5..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  General event 3  */
-	Method(_L03) {
-		/* DBGO("\\_GPE\\_L00\n") */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/ide.asl b/src/mainboard/amd/db-ft3b-lc/acpi/ide.asl
deleted file mode 100644
index 4a3eac89a339..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/acpi/ide.asl
+++ /dev/null
@@ -1,2 +0,0 @@
-/* No license required */
-/* No IDE functionality */
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl b/src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl
deleted file mode 100644
index 68609d868e2e..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Memory related values */
-Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-Name(PBLN, 0x0)	/* Length of BIOS area */
-
-Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
-Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
-Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-
-/* Some global data */
-Name(OSVR, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-Name(OSV, Ones)	/* Assume nothing */
-Name(PMOD, One)	/* Assume APIC */
-
-/* AcpiGpe0Blk */
-OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
-	Field(GP0B, ByteAcc, NoLock, Preserve) {
-	, 11,
-	USBS, 1,
-}
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/routing.asl b/src/mainboard/amd/db-ft3b-lc/acpi/routing.asl
deleted file mode 100644
index 1fb4c1dfdf2b..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/acpi/routing.asl
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Name(PR0, Package(){
-	/* NB devices */
-	/* Bus 0, Dev 0 - F16 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
-	Package(){0x0001FFFF, 0, INTB, 0 },
-	Package(){0x0001FFFF, 1, INTC, 0 },
-
-
-	/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
-	Package(){0x0002FFFF, 0, INTC, 0 },
-	Package(){0x0002FFFF, 1, INTD, 0 },
-	Package(){0x0002FFFF, 2, INTA, 0 },
-	Package(){0x0002FFFF, 3, INTB, 0 },
-
-	/* FCH devices */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, INTA, 0 },
-	Package(){0x0014FFFF, 1, INTB, 0 },
-	Package(){0x0014FFFF, 2, INTC, 0 },
-	Package(){0x0014FFFF, 3, INTD, 0 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, INTC, 0 },
-	Package(){0x0012FFFF, 1, INTB, 0 },
-
-	Package(){0x0013FFFF, 0, INTC, 0 },
-	Package(){0x0013FFFF, 1, INTB, 0 },
-
-	Package(){0x0016FFFF, 0, INTC, 0 },
-	Package(){0x0016FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, INTC, 0 },
-	Package(){0x0010FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, INTD, 0 },
-
-})
-
-Name(APR0, Package(){
-	/* NB devices in APIC mode */
-	/* Bus 0, Dev 0 - F15 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	Package(){0x0001FFFF, 0, 0, 44 },
-	Package(){0x0001FFFF, 1, 0, 45 },
-
-	/* Bus 0, Dev 2 - PCIe Bridges  */
-	Package(){0x0002FFFF, 0, 0, 24 },
-	Package(){0x0002FFFF, 1, 0, 25 },
-	Package(){0x0002FFFF, 2, 0, 26 },
-	Package(){0x0002FFFF, 3, 0, 27 },
-
-
-	/* SB devices in APIC mode */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, 0, 16 },
-	Package(){0x0014FFFF, 1, 0, 17 },
-	Package(){0x0014FFFF, 2, 0, 18 },
-	Package(){0x0014FFFF, 3, 0, 19 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, 0, 18 },
-	Package(){0x0012FFFF, 1, 0, 17 },
-
-	Package(){0x0013FFFF, 0, 0, 18 },
-	Package(){0x0013FFFF, 1, 0, 17 },
-
-	Package(){0x0016FFFF, 0, 0, 18 },
-	Package(){0x0016FFFF, 1, 0, 17 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, 0, 0x12},
-	Package(){0x0010FFFF, 1, 0, 0x11},
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, 0, 19 },
-
-})
-
-Name(PS2, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS2, Package(){
-	Package(){0x0000FFFF, 0, 0, 18 },
-	Package(){0x0000FFFF, 1, 0, 19 },
-	Package(){0x0000FFFF, 2, 0, 16 },
-	Package(){0x0000FFFF, 3, 0, 17 },
-})
-
-/* GFX */
-Name(PS4, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS4, Package(){
-	/* PCIe slot - Hooked to PCIe slot 4 */
-	Package(){0x0000FFFF, 0, 0, 24 },
-	Package(){0x0000FFFF, 1, 0, 25 },
-	Package(){0x0000FFFF, 2, 0, 26 },
-	Package(){0x0000FFFF, 3, 0, 27 },
-})
-
-/* GPP 0 */
-Name(PS5, Package(){
-	Package(){0x0000FFFF, 0, INTB, 0 },
-	Package(){0x0000FFFF, 1, INTC, 0 },
-	Package(){0x0000FFFF, 2, INTD, 0 },
-	Package(){0x0000FFFF, 3, INTA, 0 },
-})
-Name(APS5, Package(){
-	Package(){0x0000FFFF, 0, 0, 28 },
-	Package(){0x0000FFFF, 1, 0, 29 },
-	Package(){0x0000FFFF, 2, 0, 30 },
-	Package(){0x0000FFFF, 3, 0, 31 },
-})
-
-/* GPP 1 */
-Name(PS6, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS6, Package(){
-	Package(){0x0000FFFF, 0, 0, 32 },
-	Package(){0x0000FFFF, 1, 0, 33 },
-	Package(){0x0000FFFF, 2, 0, 34 },
-	Package(){0x0000FFFF, 3, 0, 35 },
-})
-
-/* GPP 2 */
-Name(PS7, Package(){
-	Package(){0x0000FFFF, 0, INTD, 0 },
-	Package(){0x0000FFFF, 1, INTA, 0 },
-	Package(){0x0000FFFF, 2, INTB, 0 },
-	Package(){0x0000FFFF, 3, INTC, 0 },
-})
-Name(APS7, Package(){
-	Package(){0x0000FFFF, 0, 0, 36 },
-	Package(){0x0000FFFF, 1, 0, 37 },
-	Package(){0x0000FFFF, 2, 0, 38 },
-	Package(){0x0000FFFF, 3, 0, 39 },
-})
-
-/* GPP 3 */
-Name(PS8, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS8, Package(){
-	Package(){0x0000FFFF, 0, 0, 40 },
-	Package(){0x0000FFFF, 1, 0, 41 },
-	Package(){0x0000FFFF, 2, 0, 42 },
-	Package(){0x0000FFFF, 3, 0, 43 },
-})
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/si.asl b/src/mainboard/amd/db-ft3b-lc/acpi/si.asl
deleted file mode 100644
index 292347127e9c..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/acpi/si.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Scope(\_SI) {
-	Method(_SST, 1) {
-		/* DBGO("\\_SI\\_SST\n") */
-		/* DBGO("   New Indicator state: ") */
-		/* DBGO(Arg0) */
-		/* DBGO("\n") */
-	}
-} /* End Scope SI */
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl b/src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl
deleted file mode 100644
index 0734c8e3c82f..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-*	Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-
-External(\_SB.APTS, MethodObj)
-External(\_SB.AWAK, MethodObj)
-
-Method(_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Clear wake status structure. */
-	Store(0, Index(WKST,0))
-	Store(0, Index(WKST,1))
-	Store(7, UPWS)
-	\_SB.APTS(Arg0)
-} /* End Method(\_PTS) */
-
-/*
-*	\_BFS OEM Back From Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		-none-
-*/
-Method(\_BFS, 1) {
-	/* DBGO("\\_BFS\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-}
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* clear USB wake up signal */
-	Store(1, USBS)
-
-	\_SB.AWAK(Arg0)
-
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl b/src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl
deleted file mode 100644
index 73077ac4d32a..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl
+++ /dev/null
@@ -1,2 +0,0 @@
-/* No license required */
-/* No thermal zone functionality */
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl b/src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl
deleted file mode 100644
index 4ebb4b64a61a..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
diff --git a/src/mainboard/amd/db-ft3b-lc/acpi_tables.c b/src/mainboard/amd/db-ft3b-lc/acpi_tables.c
deleted file mode 100644
index 20509e9d316d..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/acpi_tables.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write SB800 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-					   IO_APIC_ADDR, 0);
-
-	/* TODO: Remove the hardcode */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
-					   0xFEC20000, 24);
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
diff --git a/src/mainboard/amd/db-ft3b-lc/board_info.txt b/src/mainboard/amd/db-ft3b-lc/board_info.txt
deleted file mode 100644
index 5854f8651574..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: DB-FT3b-LC
-Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/db-ft3-lc.htm
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/amd/db-ft3b-lc/cmos.layout b/src/mainboard/amd/db-ft3b-lc/cmos.layout
deleted file mode 100644
index e1dbd9a3ddce..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/cmos.layout
+++ /dev/null
@@ -1,66 +0,0 @@
-#*****************************************************************************
-#
-#  This file is part of the coreboot project.
-#
-#  Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-#  This program is free software; you can redistribute it and/or modify
-#  it under the terms of the GNU General Public License as published by
-#  the Free Software Foundation; version 2 of the License.
-#
-#  This program is distributed in the hope that it will be useful,
-#  but WITHOUT ANY WARRANTY; without even the implied warranty of
-#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#  GNU General Public License for more details.
-#*****************************************************************************
-
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/db-ft3b-lc/devicetree.cb b/src/mainboard/amd/db-ft3b-lc/devicetree.cb
deleted file mode 100644
index dfbe3e27d7fb..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/devicetree.cb
+++ /dev/null
@@ -1,61 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2013 Advanced Micro Devices, Inc.
-# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki@gmail.com>
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/amd/pi/00730F01/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/pi/00730F01
-			device lapic 0 on  end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-
-		chip northbridge/amd/pi/00730F01
-			device pci 0.0 on  end # Root Complex
-			device pci 0.2 off end # IOMMU
-			device pci 1.0 on  end # Internal Graphics P2P bridge 0x9804
-			device pci 1.1 on  end # Internal Multimedia
-			device pci 2.0 on  end # PCIe Host Bridge
-			device pci 2.1 on  end # x4 PCIe slot
-			device pci 2.2 on  end # mPCIe slot
-			device pci 2.3 on  end # Realtek NIC
-			device pci 2.4 off end # Edge Connector
-			device pci 2.5 off end # Edge Connector
-			device pci 8.0 off end # Platform Security Processor
-		end	#chip northbridge/amd/pi/00730F01
-
-		chip southbridge/amd/pi/hudson
-			device pci 10.0 on  end # XHCI HC0
-			device pci 11.0 on  end # SATA
-			device pci 12.0 on  end # EHCI #0
-			device pci 13.0 on  end # EHCI #1
-			device pci 14.0 on  end # SMBus
-			device pci 14.2 on  end # HDA	0x4383
-			device pci 14.3 on  end # LPC	0x439d
-			device pci 14.7 on  end # SD
-			device pci 16.0 on  end # EHCI #2
-			register "sd_mode" = "3"
-		end	#chip southbridge/amd/pi/hudson
-
-		device pci 18.0 on  end
-		device pci 18.1 on  end
-		device pci 18.2 on  end
-		device pci 18.3 on  end
-		device pci 18.4 on  end
-		device pci 18.5 on  end
-
-	end #domain
-end #northbridge/amd/pi/00730F01/root_complex
diff --git a/src/mainboard/amd/db-ft3b-lc/dsdt.asl b/src/mainboard/amd/db-ft3b-lc/dsdt.asl
deleted file mode 100644
index f1ff974b49de..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/dsdt.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-#include <arch/acpi.h>
-DefinitionBlock (
-	"DSDT.AML",	/* Output filename */
-	"DSDT",		/* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
-
-	/* Globals for the platform */
-	#include "acpi/mainboard.asl"
-
-	/* Describe the USB Overcurrent pins */
-	#include "acpi/usb_oc.asl"
-
-	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
-
-	/* Describe the processor tree (\_PR) */
-	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
-		#include "acpi/routing.asl"
-
-		Device(PWRB) {
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})
-			Name(_STA, 0x0B)
-		}
-
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/pi/hudson/acpi/fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
-
-	} /* End \_SB scope */
-
-	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
-
-	/* Define the General Purpose Events for the platform */
-	#include "acpi/gpe.asl"
-
-	/* Define the Thermal zones and methods for the platform */
-	#include "acpi/thermal.asl"
-
-	/* Define the System Indicators for the platform */
-	#include "acpi/si.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/db-ft3b-lc/irq_tables.c b/src/mainboard/amd/db-ft3b-lc/irq_tables.c
deleted file mode 100644
index 465b3643d412..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/irq_tables.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c
deleted file mode 100644
index a3396593f42b..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/mainboard.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <southbridge/amd/pi/hudson/pci_devs.h>
-#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
-#include <northbridge/amd/pi/00730F01/pci_devs.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- */
-static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
-	[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
-	/* INTA# - INTH# */
-	[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
-	[0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/22 INTA-C */
-	[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
-	/* SATA */
-	[0x41] = 0x0F,
-};
-
-static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
-	[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
-	/* INTA# - INTH# */
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/20/22 INTA-C */
-	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
-	/* SATA */
-	[0x41] = 0x13,
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device.  Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01.  This index will define
- * the interrupt that it should use.  Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	/* {PCI_devfn,	{PIN A, PIN B, PIN C, PIN D}}, */
-	{GFX_DEVFN,	{PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}},			/* VGA:		01.0 */
-	{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}},			/* Audio:	01.1 */
-	{NB_PCIE_PORT1_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* x4 PCIe:	02.1 */
-	{NB_PCIE_PORT2_DEVFN,	{PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}},	/* mPCIe:	02.2 */
-	{NB_PCIE_PORT3_DEVFN,	{PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}},	/* NIC:		02.3 */
-	{XHCI_DEVFN,	{PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* XHCI:	10.0 */
-	{SATA_DEVFN,	{PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* SATA:	11.0 */
-	{OHCI1_DEVFN,	{PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI1:	12.0 */
-	{EHCI1_DEVFN,	{PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}},	/* EHCI1:	12.2 */
-	{OHCI2_DEVFN,	{PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI2:	13.0 */
-	{EHCI2_DEVFN,	{PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}},	/* EHCI2:	13.2 */
-	{SMBUS_DEVFN,	{PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* SMBUS:	14.0 */
-	{HDA_DEVFN,		{PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* HDA:		14.2 */
-	{SD_DEVFN,		{PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* SD:		14.7 */
-	{OHCI3_DEVFN,	{PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI3:	16.0 (same device as xHCI 10.0) */
-	{EHCI3_DEVFN,	{PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}},	/* EHCI3:	16.2 (same device as xHCI 10.1) */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/**********************************************
- * enable the dedicated function in mainboard.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c
deleted file mode 100644
index 40a75ad1e10d..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	/* Initialize the MP_Table */
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	/*
-	 * Type 0: Processor Entries:
-	 * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
-	 * CPU Signature (Stepping, Model, Family),
-	 * Feature Flags
-	 */
-	smp_write_processors(mc);
-
-	/*
-	 * Type 1: Bus Entries:
-	 * Bus ID, Bus Type
-	 */
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*
-	 * Type 2: I/O APICs:
-	 * APIC ID, Version, APIC Flags:EN, Address
-	 */
-	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
-	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin)				\
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	/*
-	 * Type 3: I/O Interrupt Table Entries:
-	 * Int Type, Int Polarity, Int Level, Source Bus ID,
-	 * Source Bus IRQ, Dest APIC ID, Dest PIN#
-	 */
-
-	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, int_sign, pin)				\
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
-	/* APU Internal Graphic Device */
-	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
-	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
-	/* SMBUS / ACPI */
-	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
-	/* Southbridge HD Audio */
-	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
-	/* USB */
-	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
-	PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
-	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
-	/* on board NIC & Slot PCIE */
-	PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
-	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
-	/* PCIe Lan*/
-	PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
-	/* FCH PCIe PortA */
-	PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
-	/* FCH PCIe PortB */
-	PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
-	/* FCH PCIe PortC */
-	PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
-	/* FCH PCIe PortD */
-	PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);	/* ADDR, Enable Virtual Wire */
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
deleted file mode 100644
index 77250c225927..000000000000
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <amdblocks/acpimmio.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-static void romstage_main_template(void)
-{
-	u32 val;
-
-	/*
-	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
-	 *  LpcClk[1:0]".  This following register setting has been
-	 *  replicated in every reference design since Parmer, so it is
-	 *  believed to be required even though it is not documented in
-	 *  the SoC BKDGs.  Without this setting, there is no serial
-	 *  output.
-	 */
-	pm_io_write8(0xd2, 0);
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-
-		post_code(0x31);
-		console_init();
-	}
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	pm_io_write8(0xea, 1);
-}