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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-04-18 21:13:33 +0300 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-04-21 09:39:27 +0200 |
| commit | 93b4ed91f6b1027c370da9bdd6d86664dcda671b (patch) | |
| tree | 2179e83c8bd8e3c6c361331af75275aa4dc45e00 /src/mainboard/aopen | |
| parent | 97c064f0346874dcf02d4b2700a7e7c7913b24c9 (diff) | |
| download | coreboot-93b4ed91f6b1027c370da9bdd6d86664dcda671b.tar.gz coreboot-93b4ed91f6b1027c370da9bdd6d86664dcda671b.tar.bz2 coreboot-93b4ed91f6b1027c370da9bdd6d86664dcda671b.zip | |
Intel e7505: build as separate object file
No longer include northbridge files directly in the source for
mainboard romstage.c and fix includes.
Also make required adjustments to function declarations.
Change-Id: Iafdcc0766ed44c64cc628e5935eef2c6372f5f22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/906
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/aopen')
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/romstage.c | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index ee900e9e1285..1b3e78501711 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -20,33 +20,28 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> -#include <device/pnp_def.h> #include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> #include <arch/cpu.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include <spd.h> #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/early_smbus.c" #include "southbridge/intel/i82801dx/reset.c" #include "northbridge/intel/e7505/raminit.h" -#include "northbridge/intel/e7505/debug.c" + +#include <device/pnp_def.h> #include "superio/smsc/lpc47m10x/early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/e7505/raminit.c" - void main(unsigned long bist) { static const struct mem_controller memctrl[] = { @@ -66,7 +61,7 @@ void main(unsigned long bist) report_bist_failure(bist); // If this is a warm boot, some initialization can be skipped - if (!bios_reset_detected()) { + if (!e7505_mch_is_ready()) { enable_smbus(); /* The real MCH initialisation. */ |