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| author | Patrick Georgi <pgeorgi@google.com> | 2014-11-29 10:38:17 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2014-12-02 10:25:55 +0100 |
| commit | 546953c0c553465761705fb0747964c08d634461 (patch) | |
| tree | 6cbd36b46d1230bb36a557849ac9e711a16917f1 /src/mainboard/apple/macbook21/romstage.c | |
| parent | 24cca75b47f516e2ad226c37da1e71aef5036fce (diff) | |
| download | coreboot-546953c0c553465761705fb0747964c08d634461.tar.gz coreboot-546953c0c553465761705fb0747964c08d634461.tar.bz2 coreboot-546953c0c553465761705fb0747964c08d634461.zip | |
Replace hlt with halt()
There were instances of unneeded arch/hlt.h includes,
various hlt() calls that weren't supposed to exit (but
might have) and various forms of endless loops around
hlt() calls.
All these are sorted out now: unnecessary includes are
dropped, hlt() is uniformly replaced with halt() (except
in assembly, obviously).
Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7608
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/apple/macbook21/romstage.c')
| -rw-r--r-- | src/mainboard/apple/macbook21/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 8d3fc672525c..39a8e466b0ba 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -35,6 +35,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -313,8 +314,7 @@ void main(unsigned long bist) printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); outb(0x6, 0xcf9); - while (1) - asm("hlt"); + halt(); } /* Perform some early chipset initialization required |