diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-29 22:08:01 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-29 22:08:01 +0000 |
| commit | 798ef2893c44ce3194c539c8c5db33d11e8edbac (patch) | |
| tree | 405318f804b41070e16ca6b907d65a1e27cc5071 /src/mainboard/artecgroup | |
| parent | 72bdfeb6987f9578ac7fee3f21140ab5853d6179 (diff) | |
| download | coreboot-798ef2893c44ce3194c539c8c5db33d11e8edbac.tar.gz coreboot-798ef2893c44ce3194c539c8c5db33d11e8edbac.tar.bz2 coreboot-798ef2893c44ce3194c539c8c5db33d11e8edbac.zip | |
This drops the ASSEMBLY define from romstage.c, too
(since it's not assembly code, this was a dirty hack anyways)
Also run
awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c
cut some holes into the source.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/artecgroup')
| -rw-r--r-- | src/mainboard/artecgroup/dbe61/romstage.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index fea9925d373e..d55330274d17 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -38,7 +35,6 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" - #define POST_CODE(x) outb(x, 0x80) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -47,7 +43,6 @@ #define DIMM0 0xA0 #define DIMM1 0xA2 - static int spd_read_byte(unsigned device, unsigned address) { int i; @@ -182,3 +177,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot */ return; } + |