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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-15 23:46:48 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-01-08 14:29:13 +0000 |
| commit | 6267f5dd11aa43fd0bd84f84192db4ddaffa8575 (patch) | |
| tree | 75ee8cc7fce69523e4fde510ec3330823807a40a /src/mainboard/asrock/g41c-gs/romstage.c | |
| parent | 79a7ad6dda8a5a4272b6a59cef750af2f2585dc2 (diff) | |
| download | coreboot-6267f5dd11aa43fd0bd84f84192db4ddaffa8575.tar.gz coreboot-6267f5dd11aa43fd0bd84f84192db4ddaffa8575.tar.bz2 coreboot-6267f5dd11aa43fd0bd84f84192db4ddaffa8575.zip | |
sb/intel/i82801gx: Autodisable functions based on devicetree
This removes the need to synchronize the devicetree and the romstage
writing to FD.
Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30244
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock/g41c-gs/romstage.c')
| -rw-r--r-- | src/mainboard/asrock/g41c-gs/romstage.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index e0246a88a437..e5e111059160 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -69,8 +69,7 @@ static void mb_lpc_setup(void) reg32 = RCBA32(GCS); reg32 |= (1 << 5); RCBA32(GCS) = reg32; - RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD - | FD_ACAUD | 1; + RCBA32(CG) = 0x00000001; } |