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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 21:56:37 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 18:06:27 +0000 |
| commit | 7843bd560e65b0a83e99b42bdd58dd6363656c56 (patch) | |
| tree | 0d411ba99ae94da46d3fccaf09f1208fc812bb6f /src/mainboard/asrock/g41c-gs/romstage.c | |
| parent | c583920a748fb8bd7999142433ad08641b06283d (diff) | |
| download | coreboot-7843bd560e65b0a83e99b42bdd58dd6363656c56.tar.gz coreboot-7843bd560e65b0a83e99b42bdd58dd6363656c56.tar.bz2 coreboot-7843bd560e65b0a83e99b42bdd58dd6363656c56.zip | |
nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK
There is some overlap between things done in bootblock
and romstage like setting BARs.
Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock/g41c-gs/romstage.c')
| -rw-r--r-- | src/mainboard/asrock/g41c-gs/romstage.c | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c deleted file mode 100644 index 06e13eb65230..000000000000 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> - * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pnp_ops.h> -#include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/i82801gx/i82801gx.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627dhg/w83627dhg.h> - -#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) -#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) - -void mb_lpc_setup(void) -{ - /* Set GPIOs on superio, enable UART */ - if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { - nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); - pnp_set_logical_device(SERIAL_DEV_R2); - - pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80); - pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80); - pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60); - - nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2); - nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE); - } else { - winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); - } - /* IRQ routing */ - RCBA16(D31IR) = 0x0132; - RCBA16(D29IR) = 0x0237; -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x52; -} |