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| author | Keith Hui <buurin@gmail.com> | 2023-03-23 01:11:44 -0400 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-17 13:09:04 +0000 |
| commit | a491f2fa459dca41cea8e007852b4df6da1e7fb5 (patch) | |
| tree | 909ae933155c4b1c929a393741efd73dfe0ebcfa /src/mainboard/asus/p2b | |
| parent | f97598f22fc228e3dc7e3887e9697bc50c579c97 (diff) | |
| download | coreboot-a491f2fa459dca41cea8e007852b4df6da1e7fb5.tar.gz coreboot-a491f2fa459dca41cea8e007852b4df6da1e7fb5.tar.bz2 coreboot-a491f2fa459dca41cea8e007852b4df6da1e7fb5.zip | |
nb/intel/i440bx, mb/asus/p3b-f: Abolish disable_spd()
This hook is specifically for asus/p3b-f so its mainboard code has
a chance to put SPD away after RAM init completes. What it intends
to do is done when GPO gets programmed in ramstage (and it's safe
to do so), and no other board needs this hook, so drop it.
Change-Id: Ib7874b4d2b69fdaa5f3c5a3421a62a629c4154a4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/asus/p2b')
| -rw-r--r-- | src/mainboard/asus/p2b/variants/p3b-f/romstage.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/asus/p2b/variants/p3b-f/romstage.c b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c index d72d9767e91e..6b3478bdbc03 100644 --- a/src/mainboard/asus/p2b/variants/p3b-f/romstage.c +++ b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c @@ -25,12 +25,3 @@ void enable_spd(void) { outb(0x6f, PM_IO_BASE + 0x37); } - -/* - * Disable SPD access after RAM init to allow access to SMBus/I2C offsets - * 0x48/0x49/0x2d, which is required e.g. by lm-sensors. - */ -void disable_spd(void) -{ - outb(0x67, PM_IO_BASE + 0x37); -} |