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author | Angel Pons <th3fanbus@gmail.com> | 2021-05-17 12:50:55 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-18 11:50:02 +0000 |
commit | 14b7e655bf876e8389bc83bc30e702ca3c58e845 (patch) | |
tree | 777592ce895466c3e5103f1f9cd31dadca23b160 /src/mainboard/asus/p8h61-m_pro/early_init.c | |
parent | e94cda578c6a91538c05cc8590752435136268b4 (diff) | |
download | coreboot-14b7e655bf876e8389bc83bc30e702ca3c58e845.tar.gz coreboot-14b7e655bf876e8389bc83bc30e702ca3c58e845.tar.bz2 coreboot-14b7e655bf876e8389bc83bc30e702ca3c58e845.zip |
mb/asus/p8h61-m_pro: Transform into variant setup
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO
remains identical when not adding the .config file in it.
Change-Id: Iaa53a8a1b75f4c7359e32c6cd8c8a488c5763bbe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/asus/p8h61-m_pro/early_init.c')
-rw-r--r-- | src/mainboard/asus/p8h61-m_pro/early_init.c | 57 |
1 files changed, 0 insertions, 57 deletions
diff --git a/src/mainboard/asus/p8h61-m_pro/early_init.c b/src/mainboard/asus/p8h61-m_pro/early_init.c deleted file mode 100644 index 05e87c1c6837..000000000000 --- a/src/mainboard/asus/p8h61-m_pro/early_init.c +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> - -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - -void bootblock_mainboard_early_init(void) -{ - /* Enable UART */ - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); - - /* Select SIO pin states. */ - pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); - pnp_write_config(GLOBAL_DEV, 0x24, 0x30); - pnp_write_config(GLOBAL_DEV, 0x27, 0x40); - pnp_write_config(GLOBAL_DEV, 0x2a, 0x20); - - /* Power RAM in S3. */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x10); - - pnp_set_logical_device(SERIAL_DEV); - - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); - - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} |