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| author | Angel Pons <th3fanbus@gmail.com> | 2021-05-17 17:45:54 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-20 17:49:11 +0000 |
| commit | 81c2e02bb49f517e21e89806e372d7708c54beb1 (patch) | |
| tree | d08f9501ab02381b200b1b333d77559d108297b0 /src/mainboard/asus/p8z77-v_lx2/early_init.c | |
| parent | ee5b24d232fea4bf6f097463b38f43f3e6bc9e29 (diff) | |
| download | coreboot-81c2e02bb49f517e21e89806e372d7708c54beb1.tar.gz coreboot-81c2e02bb49f517e21e89806e372d7708c54beb1.tar.bz2 coreboot-81c2e02bb49f517e21e89806e372d7708c54beb1.zip | |
mb/asus/p8z77-v_lx2: Transform into variant setup
Get ready to squash all Asus Z77 boards together, so as to factor out
some redundant code.
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-V LX2
remains identical when not adding the .config file in it.
Change-Id: I701ec4adbc65732ffc0a60d311bf07bf7f414ebf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/asus/p8z77-v_lx2/early_init.c')
| -rw-r--r-- | src/mainboard/asus/p8z77-v_lx2/early_init.c | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/src/mainboard/asus/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-v_lx2/early_init.c deleted file mode 100644 index 3a297f9e3871..000000000000 --- a/src/mainboard/asus/p8z77-v_lx2/early_init.c +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6779d/nct6779d.h> - -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) -#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - -void bootblock_mainboard_early_init(void) -{ - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); - - /* Select SIO pin states */ - pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); - pnp_write_config(GLOBAL_DEV, 0x1b, 0x70); - pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); - pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); - pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); - pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); - pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); - - /* Power RAM in S3 */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x10); - - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); - - /* Enable UART */ - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} |