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author | Felix Singer <migy@darmstadt.ccc.de> | 2018-09-17 01:26:51 +0200 |
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committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-20 11:57:11 +0000 |
commit | d959a201148dc753fcd7ba1034b78075bf779410 (patch) | |
tree | e40ba3abda8af13a5480c9c34035d90696b0b423 /src/mainboard/clevo/kbl-u/romstage.c | |
parent | 3622c0bf10ef273c7b530879d1a1af738d65ae66 (diff) | |
download | coreboot-d959a201148dc753fcd7ba1034b78075bf779410.tar.gz coreboot-d959a201148dc753fcd7ba1034b78075bf779410.tar.bz2 coreboot-d959a201148dc753fcd7ba1034b78075bf779410.zip |
mb/clevo/kbl-u: Add Clevo N130WU/N131WU
Working:
- TianoCore
- NVMe, SATA3
- USB2, USB3
- Thunderbolt
- Graphics (GOP and libgfxinit)
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
- ACPI S3
WIP:
- Documentation
Not working:
- EC ACPI (e.g. Fn keys, battery and power information)
Boots Arch Linux (Linux 5.8.12) successfully.
Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/clevo/kbl-u/romstage.c')
-rw-r--r-- | src/mainboard/clevo/kbl-u/romstage.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/clevo/kbl-u/romstage.c b/src/mainboard/clevo/kbl-u/romstage.c new file mode 100644 index 000000000000..1399d33608ff --- /dev/null +++ b/src/mainboard/clevo/kbl-u/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} |