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| author | Felix Singer <felixsinger@posteo.net> | 2020-07-29 19:57:25 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-29 20:45:29 +0000 |
| commit | 0901d03085e091a26fdc00da09a1e8e0b05adf86 (patch) | |
| tree | 8513085e64129afa84ad9a8f4c16e9e73eb92923 /src/mainboard/facebook/monolith | |
| parent | 3c0486913fea834336ebd6bf98f326aa4ba6e5c8 (diff) | |
| download | coreboot-0901d03085e091a26fdc00da09a1e8e0b05adf86.tar.gz coreboot-0901d03085e091a26fdc00da09a1e8e0b05adf86.tar.bz2 coreboot-0901d03085e091a26fdc00da09a1e8e0b05adf86.zip | |
soc/intel/skylake: Enable SATA depending on devicetree configuration
Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.
Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard/facebook/monolith')
| -rw-r--r-- | src/mainboard/facebook/monolith/devicetree.cb | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 751da3e07b89..f9a2b6632de9 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -49,18 +49,17 @@ chip soc/intel/skylake register "HeciEnabled" = "0" register "EnableLan" = "1" - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 0, \ - [2] = 0, \ - [3] = 0, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |