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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-08-19 23:52:45 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-23 15:51:47 +0000 |
| commit | eb2fc04c97c41290678161ca95a9529c5d388189 (patch) | |
| tree | 2065ef51775dfa7c65172ce0011d16164bb5620a /src/mainboard/foxconn/d41s/dsdt.asl | |
| parent | a2c0cf5dfe4c2666cf4302c58360c45819b1f769 (diff) | |
| download | coreboot-eb2fc04c97c41290678161ca95a9529c5d388189.tar.gz coreboot-eb2fc04c97c41290678161ca95a9529c5d388189.tar.bz2 coreboot-eb2fc04c97c41290678161ca95a9529c5d388189.zip | |
mb/foxconn/d41s: Add mainboard
This supports the Foxconn d41s, d42s, d51s, d52s.
The following is tested (SeaBIOS 1.12 + Linux 4.9) and works:
- COM1
- S3 resume (with SeaBIOS needs sercon disabled)
- Native graphic init on VGA output
- SATA
- USB
- Ethernet
- PS2 keyboard
The base for this mainboard port was the Intel D510MO port.
Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28227
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/foxconn/d41s/dsdt.asl')
| -rw-r--r-- | src/mainboard/foxconn/d41s/dsdt.asl | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl new file mode 100644 index 000000000000..621b87dc7a25 --- /dev/null +++ b/src/mainboard/foxconn/d41s/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + #include <cpu/intel/speedstep/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/pineview/acpi/pineview.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} |