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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-08-15 20:59:09 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-14 21:43:25 +0000 |
| commit | b451df2f400ba12fff440247330f8b57a93034bd (patch) | |
| tree | 8bb52821a42aaaea2e614910d97b1ae4e690b7c2 /src/mainboard/foxconn | |
| parent | e4a016ff17b455a8acd0ea72b30caabb622ce224 (diff) | |
| download | coreboot-b451df2f400ba12fff440247330f8b57a93034bd.tar.gz coreboot-b451df2f400ba12fff440247330f8b57a93034bd.tar.bz2 coreboot-b451df2f400ba12fff440247330f8b57a93034bd.zip | |
mb/*/*/romstage.c: Clean up targets with i82801gx
Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/foxconn')
| -rw-r--r-- | src/mainboard/foxconn/g41s-k/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index ba07e45e9953..5ea41ea1945e 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -78,7 +78,7 @@ static void ich7_enable_lpc(void) COMB_LPC_EN | COMA_LPC_EN); /* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */ - pci_write_config32(LPC_DEV, 0x84, 0x003c0a01); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01); } void mainboard_romstage_entry(unsigned long bist) |