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| author | Patrick Georgi <patrick.georgi@secunet.com> | 2011-01-27 07:39:38 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2011-01-27 07:39:38 +0000 |
| commit | a470019b7a19e164b5dc93b1d541dc4158edbeda (patch) | |
| tree | 48156b3fb7f795cbe3241f787b642460aa03a29d /src/mainboard/getac/p470/devicetree.cb | |
| parent | a5c949eff288af3eb4caffec57a3724c497150de (diff) | |
| download | coreboot-a470019b7a19e164b5dc93b1d541dc4158edbeda.tar.gz coreboot-a470019b7a19e164b5dc93b1d541dc4158edbeda.tar.bz2 coreboot-a470019b7a19e164b5dc93b1d541dc4158edbeda.zip | |
Add a new CMOS variable which triggers activation of the
LPT port. With the CMOS variable set, LPT is found by SeaBIOS,
with the variable reset, it's not.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/getac/p470/devicetree.cb')
| -rw-r--r-- | src/mainboard/getac/p470/devicetree.cb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 26939772ada6..2929cbee5b30 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -86,7 +86,9 @@ chip northbridge/intel/i945 device pnp 2e.1 off # ACPI PM end # 2e.2 does not exist - device pnp 2e.3 off # Parallel port + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 end device pnp 2e.4 on # COM1 io 0x60 = 0x3f8 |